On Wed, Apr 30, 2008 at 08:24:48PM -0700, Linus Torvalds wrote: > > On Thu, 1 May 2008, Nick Piggin wrote: > > But I'm surprised that two writes to the same cacheline (different > > words) can be reordered. Of course write buffers are technically outside > > the coherency domain, but I would have thought any implementation will > > actually treat writes to the same line as aliasing. Is there a counter > > example? > > I don't know if anybody does it, but no, normally I would *not* expect any > alias logic to have anything to do with cachelines. Aliasing within a > cacheline is so common (spills to the stack, if nothing else) that if the > CPU has some write buffer alias logic, I'd expect it to be byte or perhaps > word-granular. > > So I think that at least in theory it is quite possible that a later write > hits the same cacheline first, just because the write data or address got > resolved first and the architecture allows out-of-order memory accesses. I guess it is possible. But at least in the case of write address, you'd have to wait for later stores anyway in order to do the alias detection, which might be the most common case. For other dependencies yes, although I would have thought that you'd be better off to wait for the earlier write and so they can be combined into a single cache transaction. The easy part of stores is queueing them, the hard part is moving them out to cache. Anyway I'm speculating at this point. You do raise a valid issue, so obviously we can't make any such assumptions without verifying it on a per-arch basis ;) I'm just interested to know whether this happens on any CPU we run on. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
