On Thu, 1 May 2008, Nick Piggin wrote: > > > > Of course, on x86, the write ordering is strictly defined, and even if the > > CPU reorders writes they are guaranteed to never show up re-ordered, so > > this is not an issue. But I wanted to point out that memory ordering is > > *not* just about cachelines, and being in the same cacheline is no > > guarantee of anything, even if it can have *some* effects. > > Well it is a guarantee about cache coherency presumably, but I guess > you're taking that for granted. Yes, I'm taking cache coherency for granted, I don't think it's worth even worrying about non-coherent cases. > But I'm surprised that two writes to the same cacheline (different > words) can be reordered. Of course write buffers are technically outside > the coherency domain, but I would have thought any implementation will > actually treat writes to the same line as aliasing. Is there a counter > example? I don't know if anybody does it, but no, normally I would *not* expect any alias logic to have anything to do with cachelines. Aliasing within a cacheline is so common (spills to the stack, if nothing else) that if the CPU has some write buffer alias logic, I'd expect it to be byte or perhaps word-granular. So I think that at least in theory it is quite possible that a later write hits the same cacheline first, just because the write data or address got resolved first and the architecture allows out-of-order memory accesses. Whether you'll ever see it in practice, I don't know. Never on x86, of course. Linus -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
