On 29/09/2022 23:29, Rick Edgecombe wrote: > From: Yu-cheng Yu <yu-cheng.yu@xxxxxxxxx> > > Processors sometimes directly create Write=0,Dirty=1 PTEs. Do they? (Rhetorical) Yes, this is a relevant anecdote for why CET isn't available on pre-TGL parts, but it one of the more wrong things to have as the first sentence of this commit message. The point you want to express is that under the CET-SS spec, R/O+Dirty has a new meaning as type=shstk, so stop using this bit combination for existing mappings. I'm not even sure it's relevant to note that CET capable processors can set D on a R/O mapping, because that depends on !CR0.WP which in turn prohibits CR4.CET being enabled. ~Andrew
