On Thu, Sep 29, 2022 at 03:29:05PM -0700, Rick Edgecombe wrote:
> From: Yu-cheng Yu <yu-cheng.yu@xxxxxxxxx>
>
> Processors sometimes directly create Write=0,Dirty=1 PTEs. These PTEs are
> created by software. One such case is that kernel read-only pages are
> historically set up as Dirty.
>
> New processors that support Shadow Stack regard Write=0,Dirty=1 PTEs as
> shadow stack pages. When CR4.CET=1 and IA32_S_CET.SH_STK_EN=1, some
> instructions can write to such supervisor memory. The kernel does not set
> IA32_S_CET.SH_STK_EN, but to reduce ambiguity between shadow stack and
> regular Write=0 pages, removed Dirty=1 from any kernel Write=0 PTEs.
>
> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@xxxxxxxxx>
> Co-developed-by: Rick Edgecombe <rick.p.edgecombe@xxxxxxxxx>
> Signed-off-by: Rick Edgecombe <rick.p.edgecombe@xxxxxxxxx>
> Cc: "H. Peter Anvin" <hpa@xxxxxxxxx>
> Cc: Kees Cook <keescook@xxxxxxxxxxxx>
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>
> Cc: Christoph Hellwig <hch@xxxxxx>
> Cc: Andy Lutomirski <luto@xxxxxxxxxx>
> Cc: Ingo Molnar <mingo@xxxxxxxxxx>
> Cc: Borislav Petkov <bp@xxxxxxxxx>
> Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
>
> ---
>
> v2:
> - Normalize PTE bit descriptions between patches
>
> arch/x86/include/asm/pgtable_types.h | 6 +++---
> arch/x86/mm/pat/set_memory.c | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
> index aa174fed3a71..ff82237e7b6b 100644
> --- a/arch/x86/include/asm/pgtable_types.h
> +++ b/arch/x86/include/asm/pgtable_types.h
> @@ -192,10 +192,10 @@ enum page_cache_mode {
> #define _KERNPG_TABLE (__PP|__RW| 0|___A| 0|___D| 0| 0| _ENC)
> #define _PAGE_TABLE_NOENC (__PP|__RW|_USR|___A| 0|___D| 0| 0)
> #define _PAGE_TABLE (__PP|__RW|_USR|___A| 0|___D| 0| 0| _ENC)
> -#define __PAGE_KERNEL_RO (__PP| 0| 0|___A|__NX|___D| 0|___G)
> -#define __PAGE_KERNEL_ROX (__PP| 0| 0|___A| 0|___D| 0|___G)
> +#define __PAGE_KERNEL_RO (__PP| 0| 0|___A|__NX| 0| 0|___G)
> +#define __PAGE_KERNEL_ROX (__PP| 0| 0|___A| 0| 0| 0|___G)
> #define __PAGE_KERNEL_NOCACHE (__PP|__RW| 0|___A|__NX|___D| 0|___G| __NC)
> -#define __PAGE_KERNEL_VVAR (__PP| 0|_USR|___A|__NX|___D| 0|___G)
> +#define __PAGE_KERNEL_VVAR (__PP| 0|_USR|___A|__NX| 0| 0|___G)
> #define __PAGE_KERNEL_LARGE (__PP|__RW| 0|___A|__NX|___D|_PSE|___G)
> #define __PAGE_KERNEL_LARGE_EXEC (__PP|__RW| 0|___A| 0|___D|_PSE|___G)
> #define __PAGE_KERNEL_WP (__PP|__RW| 0|___A|__NX|___D| 0|___G| __WP)
> diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
> index 1abd5438f126..ed9193b469ba 100644
> --- a/arch/x86/mm/pat/set_memory.c
> +++ b/arch/x86/mm/pat/set_memory.c
> @@ -1977,7 +1977,7 @@ int set_memory_nx(unsigned long addr, int numpages)
>
> int set_memory_ro(unsigned long addr, int numpages)
> {
> - return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
> + return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW | _PAGE_DIRTY), 0);
> }
Hm. Do we need to modify also *_wrprotect() helpers to clear dirty bit?
I guess not (at least without a lot of audit), as we risk loosing dirty
bit on page cache pages. But why is it safe? Do we only care about about
kernel PTEs here? Userspace Write=0,Dirty=1 PTEs handled as before?
> int set_memory_rw(unsigned long addr, int numpages)
> --
> 2.17.1
>
--
Kiryl Shutsemau / Kirill A. Shutemov
