On 08/23/2018 02:02 PM, Mikulas Patocka wrote: > > > On Wed, 22 Aug 2018, Richard Henderson wrote: > >> On 08/22/2018 01:42 PM, Mikulas Patocka wrote: >>> unsigned long flags = swpipl(IPL_MAX); >>> >>> - barrier(); >>> + mb(); >> >> Maybe, but I doubt it makes a difference in practice. >> >> The swpipl is a transition through PALcode, and the >> instruction queue will have been flushed into and out >> of PALmode. > > Architecturally, PAL calls aren't memory barriers. I realize that of course. > It's hard to tell whether they are in practice. Indeed. Two pipeline stalls, plus other code in between to actually perform the interrupt masking. While it's theoretically possible a memory operation might still be in flight... I think you'd have to work hard to demonstrate it. > The possible problem here is reordering inside the chipset, not inside the > CPU (ev45 is in-order). And the chipset doesn't care whether the CPU is > executing inside PAL or not. AFAIR, mb does not order data within the chipset, only within the cpu. And furthermore that the chipset is always in-order. r~
