BTW - this doesn't fix the hang, but the code seems to be wrong here. The
write to the hae register is not ordered with previous writel,
writel_relaxed or readl_relaxed to device memory that is mapped by hae.
Suppose that writel is followed by readl and readl changes the hae
register. The write to the hae register is not ordered with the previous
writel. This patch adds a barrier.
Signed-off-by: Mikulas Patocka <mpatocka@xxxxxxxxxx>
---
arch/alpha/include/asm/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux-2.6/arch/alpha/include/asm/io.h
===================================================================
--- linux-2.6.orig/arch/alpha/include/asm/io.h 2018-05-31 18:04:35.896000000 +0200
+++ linux-2.6/arch/alpha/include/asm/io.h 2018-08-22 22:33:59.130000000 +0200
@@ -39,7 +39,7 @@ extern inline void __set_hae(unsigned lo
{
unsigned long flags = swpipl(IPL_MAX);
- barrier();
+ mb();
alpha_mv.hae_cache = new_hae;
*alpha_mv.hae_register = new_hae;
