On Mon, May 11, 2020 at 03:04:57PM +0200, Andrew Lunn wrote: > > NXP's LX2160ARDB platform currently has the following MDIO-PHY connection. > > > > MDIO-1 ==> one 40G PHY, two 1G PHYs(C45), two 10G PHYs(C22) > > MDIO-2 ==> one 25G PHY > > It has been suggested that ACPI only support a one to one > mapping. Each MAC has one MDIO bus, with one PHY on it. KISS. > > This clearly does not work for your hardware. So not only do we need > to solve how PHY properties are described, we also need an equivalent > of phy-handle, so a MAC can indicate which PHY it is connected to. I'd suggest that doesn't work for a lot of hardware. It won't work for the Macchiatobin for example, where there are two Clause 45 NBASE-T PHYs on one MDIO bus. The same is likely true on the LX2160A - there can be multiple ethernet interfaces, but IIRC only two external MDIO buses that one can hang PHYs off of. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up
