>> 1) Some banks may not support CMCI at all (bit 30 in MCi_CTL2 register
>> ignores attempts to enable). For these banks Linux should poll.
>
> That's the detection method, try setting bit 30 to see if it sticks?
Yes. See Intel SDM Vol 3B section "15.3.2.5 IA32_MCi_CTL2 MSRs"
>> 2) BIOS may support generation of APEI records for certain classes of
>> errors. HEST will say which banks are affected, and if we prefer APEI,
>> we should disable CMCI for these banks (and not poll them).
> Ok, so it looks like code should iterate over those and remove them from
> the mce_banks list we pass on to machine_check_poll.
I think so. the mce_banks bitmaps keep track of which cpu is responsible
for checking a bank (because banks can be shared by multiple cpus ... e.g.
socket level bank is same to all logical cpus on a package. Core level bank
is shared by just the two hyperthreads on a core). If we trust APEI to handle
things, then the bank shouldn't be owned by any cpu.
>> 3) Some banks may support CMCI, but don't have BIOS support to
>> generate APEI records. We should continue to enable CMCI for these.
>
> How do you get that out of the HEST? The inability to generate APEI
> records.
Perhaps just by whatever banks you find left over after iterating the ones
that *are* in HEST? There isn't an explicit list.
-Tony
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