Eric W. Biederman wrote: > > Looking at the coreboot source. It is indeed defined for Nvidia, SIS, > AMD and several others. > > A lot of boards use: > outb(0x02, 0xcf9); > outb(0x06, 0xcf9); > > Instead of just writing a plain 6. I think at least on some machines > there is a requirement for a low to hight transition. > That is correct; that is what my patch has, with a 50 µs delay in between (I also don't touch the ~6 bits.) > > Right. The only scary question is will a motherboard hang if you write > to 0xcf9. If we don't know of an example where writing to 0xcf9 will prevent > us from getting to the next reset method then adding a generic 0xcf9 is > safe. > It would be highly surprising, except possibly on pre-PCI systems, which is why my patch skips CF9 if the standard PCI ports are not detected. Although CF9 isn't defined in the PCI spec, it falls in the PCI configuration port range. -hpa -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
