On Wed, Jun 19, 2024 at 07:32:18PM +0800, yunhui cui wrote: > Hi Sunil, > > On Mon, Jun 17, 2024 at 9:14 PM Yunhui Cui <cuiyunhui@xxxxxxxxxxxxx> wrote: > > > > After adding ACPI support to populate_cache_leaves(), RISC-V can build > > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT > > configuration. > > > > Signed-off-by: Yunhui Cui <cuiyunhui@xxxxxxxxxxxxx> > > Reviewed-by: Jeremy Linton <jeremy.linton@xxxxxxx> > > Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx> > > Reviewed-by: Sunil V L <sunilvl@xxxxxxxxxxxxxxxx> > > --- > > arch/riscv/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 9f38a5ecbee3..1b4c310a59fb 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -13,6 +13,7 @@ config 32BIT > > config RISCV > > def_bool y > > select ACPI_GENERIC_GSI if ACPI > > + select ACPI_PPTT if ACPI > > select ACPI_REDUCED_HARDWARE_ONLY if ACPI > > select ARCH_DMA_DEFAULT_COHERENT > > select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION > > -- > > 2.20.1 > > > > Gentle ping. > Actually, my RB is still valid. Anyway, here again. Reviewed-by: Sunil V L <sunilvl@xxxxxxxxxxxxxxxx> Thanks, Sunil
