Dave Jiang wrote: > Export qtg_id sysfs attributes for the CXL memory device. The QTG ID > should show up as /sys/bus/cxl/devices/memX/qtg_id. The QTG ID is > retrieved via _DSM after supplying the caluclated bandwidth and latency > for the entire CXL path from device to the CPU. This ID is used to match > up to the root decoder QTG ID to determine which CFMWS the memory range > of a hotplugged CXL mem device should be assigned under. > > While there may be multiple DSMAS exported by the device CDAT, the driver > will only expose the first QTG ID in sysfs for now. In the future when > multiple QTG IDs are necessary, they can be exposed. [1] > > [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab > > Suggested-by: Dan Williams <dan.j.williams@xxxxxxxxx> > Signed-off-by: Dave Jiang <dave.jiang@xxxxxxxxx> > --- > Documentation/ABI/testing/sysfs-bus-cxl | 11 +++++++++++ > drivers/cxl/core/memdev.c | 15 +++++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl > index 471ac9a37078..a018f0a21aca 100644 > --- a/Documentation/ABI/testing/sysfs-bus-cxl > +++ b/Documentation/ABI/testing/sysfs-bus-cxl > @@ -58,6 +58,17 @@ Description: > affinity for this device. > > > +What: /sys/bus/cxl/devices/memX/qtg_id Oh, I was still thinking there would be a qtg_id per partition type, just not a multiple qtg_ids per partition type until it is clear that those are something hardware vendors are actually going to ship, but I expect a DSMAS per partition type will be common. So I was expecting: /sys/bus/cxl/devices/memX/{ram,pmem}/qtg_id ...and when the DCD patches land that expands to: /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_id If someone builds a device with multiple performance classes per partition then it would become: /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_id /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_id[1..n] /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_range/ /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_range[1..n]/ ...where I am using CXL 3.0 Figure 9-24 "DCD DPA Space Example" as the delineation of the possible partition types.
