Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem

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To: Pierre Gondois <pierre.gondois@xxxxxxx>
Subject: Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem
From: Sudeep Holla <sudeep.holla@xxxxxxx>
Date: Tue, 8 Nov 2022 16:03:23 +0000
Cc: linux-kernel@xxxxxxxxxxxxxxx, Catalin Marinas <catalin.marinas@xxxxxxx>, Will Deacon <will@xxxxxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, Palmer Dabbelt <palmer@xxxxxxxxxxx>, Albert Ou <aou@xxxxxxxxxxxxxxxxx>, "Rafael J. Wysocki" <rafael@xxxxxxxxxx>, Len Brown <lenb@xxxxxxxxxx>, Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, Gavin Shan <gshan@xxxxxxxxxx>, Krzysztof Wilczyński <kw@xxxxxxxxx>, Jani Nikula <jani.nikula@xxxxxxxxx>, Jakub Kicinski <kuba@xxxxxxxxxx>, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, linux-riscv@xxxxxxxxxxxxxxxxxxx, linux-acpi@xxxxxxxxxxxxxxx
In-reply-to: <20221108110424.166896-2-pierre.gondois@arm.com>
References: <20221108110424.166896-1-pierre.gondois@arm.com> <20221108110424.166896-2-pierre.gondois@arm.com>

On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> Riscv's implementation of init_of_cache_level() is following
> the Devicetree Specification v0.3 regarding caches, cf.:
> - s3.7.3 'Internal (L1) Cache Properties'
> - s3.8 'Multi-level and Shared Cache Nodes'
> 
> Allow reusing the implementation by moving it.
>

Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx>

-- 
Regards,
Sudeep

Follow-Ups:
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References:
- [PATCH 0/5] arch_topology: Build cacheinfo from primary CPU
  - From: Pierre Gondois
- [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic OF implem
  - From: Pierre Gondois

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