On Thu, Oct 13, 2022 at 06:45:44PM +0200, Peter Zijlstra wrote:
> Borislav is thinking too much x86. Failed cmpxchg() does indeed not
> imply any memory ordering for all architectures -- and while the memory
> clobber (aka. barrier()) is equivalent to an smp_wmb() on x86, that most
> certainly doesn't hold for non x86 code.
Right, but the patch was addied by an Intel person, CCed:
152cef40a808 ("ACPI, APEI, GHES, Error records content based throttle")a
So I don't think he was thinking about ARM when doing that.
And that commit message doesn't say one whit why that memory barrier is
needed there.
Reading that comment, it sounds like he wanted a hw memory barrier -
MFENCE - but I don't see how normal data dependency wouldn't enforce the proper order
already...
So that barrier looks out of place there.
Btw, this is the next perfect example why I'm asking people to write
proper commit messages so that when we do git archeology later, we can
figure out why something was done the way it has been.
And in this case, we can't. ;-\
Because writing proper commit messages is for losers. Yeah, right.</sarcasm>
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
