On Mon, 2021-05-31 at 08:46 +0200, Christoph Hellwig wrote: > On Fri, May 28, 2021 at 11:02:34AM -0500, Mario Limonciello wrote: > > The documentation around the StorageD3Enable property hints that it > > should be made on the PCI device. This is where newer AMD systems > > set > > the property and it's required for S0i3 support. > > > > So rather than look for nodes of the root port only present on > > Intel > > systems, switch to the companion ACPI device for all systems. > > David Box from Intel indicated this should work on Intel as well. > > I think we need to wait for the confirmation from David. I've tested one configuration remotely already and it works. I've got one more to test. I'll know by tomorrow. David
