On Sun, May 12, 2013 at 04:48:28PM +0300, Abel Gordon wrote: > > > Kashyap Chamarthy <kashyap.cv@xxxxxxxxx> wrote on 12/05/2013 04:06:40 PM: > > > > > Note shadow vmcs is disabled unless you have a processor > > > that supports this feature. Do you ?! > > > > Yes, I noted this in my previous email. I'm using Intel Haswell. > > > > Here's the info from MSR bits on the machine(From `Table 35-3`, MSRs > > in Procesors Based on Intel Core Microarchitecture, `Volume 3C of the > > SDM ) > > -------------------------------------------- > > # Read msr value > > $ rdmsr 0x48B > > 7cff00000000 > > > > # Check Shadow VMCS is enabled: > > $ rdmsr 0x00000485 > > 300481e5 > > -------------------------------------------- > > > > And, on the Kernel command line: > > -------------------------------------------- > > # nested > > $ cat /sys/module/kvm_intel/parameters/nested > > Y > > > > # shadow VMCS > > $ cat /sys/module/kvm_intel/parameters/enable_shadow_vmcs > > Y > > -------------------------------------------- > > Yep, shadow-vmcs enabled :) > > > > Just for reference, here's the detailed procedure I noted while > > testing it on Haswell -- > > https://raw.github.com/kashyapc/nvmx-haswell/master/SETUP-nVMX.rst > > > > Also note you can disable > > > shadow-vmcs using the kvm-intel kernel module parameter > > > "enable_shadow_vmcs". > > > > Yes, to test w/o shadow VMCS, I disabled it by adding "options > > kvm-intel enable_shadow_vmcs=y" to /etc/modprobe.d/dist.conf & reboot > > the host. > > I assume you meant enable_shadow_vmcs=n :) > > Small question: did you try to disable apicv/posted interrupts at L0 ? > (for L1 you can't enable these features because they are not emulated) > AFAIK Haswell does not have apicv/posted interrupts. Not the one I have access to anyway. -- Gleb. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
