Intel's definition of "edge triggered" means: "asserted with a
low-to-high transition at the time an interrupt is registered
and then kept high until the interrupt is served via one of the
EOI mechanisms or goes away unhandled."
So the only difference between edge triggered and level triggered
is in the leading edge, with no difference in the trailing edge.
This bug manifested itself when the guest was Microport UNIX
System V/386 v2.1 (ca. 1987), because it would sometimes mask
off IRQ14 in the slave IMR after it had already been asserted.
The master would still try to deliver an interrupt to the CPU even
though IRQ2 had dropped again, resulting in a spurious interupt
(IRQ15) and a panicked UNIX kernel.
Signed-off-by: Matthew Ogilvie <mmogilvi_qemu@xxxxxxxxxxxx>
---
arch/x86/kvm/i8259.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index cc31f7c..76d8dc1 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -111,8 +111,10 @@ static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
s->irr |= mask;
}
s->last_irr |= mask;
- } else
+ } else {
+ s->irr &= ~mask;
s->last_irr &= ~mask;
+ }
return (s->imr & mask) ? -1 : ret;
}
@@ -169,14 +171,10 @@ static void pic_update_irq(struct kvm_pic *s)
{
int irq2, irq;
+ /* slave PIC notifies master PIC via IRQ2 */
irq2 = pic_get_irq(&s->pics[1]);
- if (irq2 >= 0) {
- /*
- * if irq request by slave pic, signal master PIC
- */
- pic_set_irq1(&s->pics[0], 2, 1);
- pic_set_irq1(&s->pics[0], 2, 0);
- }
+ pic_set_irq1(&s->pics[0], 2, irq2 >= 0);
+
irq = pic_get_irq(&s->pics[0]);
pic_irq_request(s->kvm, irq >= 0);
}
--
1.7.10.2.484.gcd07cc5
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