On Thu, Nov 15, 2012 at 12:31:05PM -0800, Will Auld wrote:
> CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
>
> Basic design is to emulate the MSR by allowing reads and writes to the
> hypervisor vcpu specific locations to store the value of the emulated MSRs.
> In this way the IA32_TSC_ADJUST value will be included in all reads to
> the TSC MSR whether through rdmsr or rdtsc.
>
> As this is a new MSR that the guest may access and modify its value needs
> to be migrated along with the other MRSs. The changes here are specifically
> for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
> for migrating its value.
>
> Signed-off-by: Will Auld <will.auld@xxxxxxxxx>
> ---
> target-i386/cpu.h | 4 +++-
> target-i386/kvm.c | 15 +++++++++++++++
> target-i386/machine.c | 21 +++++++++++++++++++++
> 3 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index aabf993..7ca99c0 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -284,6 +284,7 @@
> #define MSR_IA32_APICBASE_BSP (1<<8)
> #define MSR_IA32_APICBASE_ENABLE (1<<11)
> #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
> +#define MSR_TSC_ADJUST 0x0000003b
> #define MSR_IA32_TSCDEADLINE 0x6e0
>
> #define MSR_MTRRcap 0xfe
> @@ -701,6 +702,7 @@ typedef struct CPUX86State {
> uint64_t async_pf_en_msr;
>
> uint64_t tsc;
> + uint64_t tsc_adjust;
> uint64_t tsc_deadline;
>
> uint64_t mcg_status;
> @@ -979,7 +981,7 @@ static inline CPUX86State *cpu_init(const char *cpu_model)
> #define cpu_list_id x86_cpu_list
> #define cpudef_setup x86_cpudef_setup
>
> -#define CPU_SAVE_VERSION 12
> +#define CPU_SAVE_VERSION 13
With the subsection, increasing CPU_SAVE_VERSION is not necessary.
Otherwise looks fine.
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