On Thu, 18 Oct 2012, Avi Kivity wrote:
On 10/18/2012 11:35 AM, Gleb Natapov wrote:
You misunderstood the description. V_INTR_MASKING=1 means that CR8 writes
are not propagated to real HW APIC.
But KVM does not trap access to CR8 unconditionally. It enables CR8
intercept only when there is pending interrupt in IRR that cannot be
immediately delivered due to current TPR value. This should eliminate 99%
of CR8 intercepts.
Right. You will need to expose the alternate encoding of cr8 (IIRC lock
mov reg, cr0) on AMD via cpuid, but otherwise it should just work. Be
aware that this will break cross-vendor migration.
Thanks for the clarifications. I will try that.
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