On 1 September 2012 20:40, Christoffer Dall <c.dall@xxxxxxxxxxxxxxxxxxxxxx> wrote: > On Sep 1, 2012, at 6:25 AM, Peter Maydell <peter.maydell@xxxxxxxxxx> wrote: >> On 1 September 2012 10:16, Avi Kivity <avi@xxxxxxxxxx> wrote: >>> On 08/29/2012 11:21 AM, Rusty Russell wrote: >>>> Peter Maydell wrote: >>>>> ...but if we do go this path, you can't use coprocessor 0 >>>>> to mean core register -- cp0 could be a valid coprocessor >>>>> (the ARM ARM reserves cp0..cp7 for "vendor specific features"). >>>>> Use something outside 0..15. >>>> >>>> OK, changed that too (16). >> >>> And tomorrow they will add 16. >> >> Not possible in the instruction encoding :-) We haven't used >> anywhere near all the coprocessors (even given we've let the >> vendors have 0..7, ARM itself uses only 10 and 11 for the FPU, >> 14 for debug/perf and 15 for system control (and 14 and 15 still >> have lots of spare space). > Yeah, but folding core registers under coprocessors feels just > too fishy, so I think we should have a separate field. I never really thought of the top half of the index encoding as being particularly a coprocessor-number specific thing in the first place. It's just 16 bits of "what is this thing anyway?", where each coprocessor gets a bit of the space, and so will the GIC, and the VFP regs, and so on. We just happened to use 0..15 of the "what is this?" space for cp0..cp15. (Incidentally, the term "coprocessor" is now basically just a historical artefact. The bits of the CPU you get at via the "coprocessor" registers and instruction encoding space are not separate functional units, they're part of the core.) -- PMM -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
