On Thu, May 31, 2012 at 12:57:10PM +0300, Gleb Natapov wrote:
> > @@ -1345,17 +1437,40 @@ void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
> > apic_set_tpr(vcpu->arch.apic, data & 0xff);
> > }
> >
> > +/*
> > + * apic_sync_pv_eoi_to_guest - called before vmentry
> > + *
> > + * Detect whether it's safe to enable PV EOI and
> > + * if yes do so.
> > + */
> > +static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
> > + struct kvm_lapic *apic)
> > +{
> > + if (!pv_eoi_enabled(vcpu) ||
> > + /* IRR set or many bits in ISR: could be nested. */
> > + unlikely(apic->irr_pending) ||
> > + unlikely(apic->isr_count != 1) ||
> Remind me why pv_eoi should not be set if there is more than one isr?
There's a comment below: it might be safe but
we do not bother: no easy way to know which interrupt
has higher priority.
In my testing more than one bit almost never happens in practice so not
worth optimizing for.
>
> > + /* Cache not set: safe but we don't bother. */
> > + unlikely(apic->isr_cache == -1) ||
> > + /* Need EOI to update ioapic. */
> > + unlikely(kvm_ioapic_handles_vector(vcpu->kvm, apic->isr_cache)))
> > + return;
> > +
> > + pv_eoi_set_pending(apic->vcpu);
> > +}
> > +
> apic_sync_pv_eoi_to_guest() is not paired with
> apic_sync_pv_eoi_from_guest() if event injection is canceled.
> You can enter guest with stale pv_eoi bit.
Never. The pv_eoi bit is cleared on each exit.
It will stay cleared unless we set it here.
I will add a comment.
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