On Tue, 2012-01-31 at 14:13 -0700, Alex Williamson wrote:
> On Tue, 2012-01-31 at 14:45 +0200, Avi Kivity wrote:
> > On 01/28/2012 04:21 PM, Alex Williamson wrote:
> > > Stop using compatibility mode and at the same time fix available
> > > access sizes. The PCI spec indicates that the MSI-X table may
> > > only be accessed as DWORD or QWORD.
> > >
> > >
> > > static const MemoryRegionOps msix_mmio_ops = {
> > > - .old_mmio = {
> > > - .read = { msix_mmio_readb, msix_mmio_readw, msix_mmio_readl, },
> > > - .write = { msix_mmio_writeb, msix_mmio_writew, msix_mmio_writel, },
> > > - },
> > > + .read = msix_mmio_read,
> > > + .write = msix_mmio_write,
> > > .endianness = DEVICE_NATIVE_ENDIAN,
> > > + .impl = {
> > > + .min_access_size = 4,
> > > + .max_access_size = 8,
> > > + },
> > > };
> > >
> >
> > .impl.min_access_size = 4 means the core will convert 1-byte I/O to
> > 4-byte I/O (using rmw if needed). That's not what we want, I think you
> > can leave it at 1 and explicitly ignore small accesses in the callbacks.
> >
> > Have you tested 8-byte I/O? This is the first user. Don't you need to
> > set .valid.max_access_size?
>
> I have not explicitly tested 8-byte I/O, figured it might just work.
Tested, it gets split into 4-byte accesses by cpu_physical_memory_rw().
It's trivial to add 8-byte access there and they get all the way through
the memory API intact. I expect there's a lot more than that to make
exec.c quad word access clean though. I'll leave the 8-byte access in
place in case it's a good test case. Thanks,
Alex
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