[PATCH 2/2 v2] KVM: x86 emulator: Use opcode::execute for Group 2 instructions

[Takuya Yoshikawa <yoshikawa.takuya@xxxxxxxxxxxxx>]

Group 2: C0, C1, D0, D1, D2, D3

Split em_grp2() into em_rol(), em_ror(), ..., and register them.

Signed-off-by: Takuya Yoshikawa <yoshikawa.takuya@xxxxxxxxxxxxx>
---
 arch/x86/kvm/emulate.c |   91 +++++++++++++++++++++++++++++-------------------
 1 files changed, 55 insertions(+), 36 deletions(-)

diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 2f287f4..5e7c734 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -1676,32 +1676,45 @@ static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
 	return X86EMUL_CONTINUE;
 }
 
-static int em_grp2(struct x86_emulate_ctxt *ctxt)
+static int em_rol(struct x86_emulate_ctxt *ctxt)
 {
-	switch (ctxt->modrm_reg) {
-	case 0:	/* rol */
-		emulate_2op_SrcB(ctxt, "rol");
-		break;
-	case 1:	/* ror */
-		emulate_2op_SrcB(ctxt, "ror");
-		break;
-	case 2:	/* rcl */
-		emulate_2op_SrcB(ctxt, "rcl");
-		break;
-	case 3:	/* rcr */
-		emulate_2op_SrcB(ctxt, "rcr");
-		break;
-	case 4:	/* sal/shl */
-	case 6:	/* sal/shl */
-		emulate_2op_SrcB(ctxt, "sal");
-		break;
-	case 5:	/* shr */
-		emulate_2op_SrcB(ctxt, "shr");
-		break;
-	case 7:	/* sar */
-		emulate_2op_SrcB(ctxt, "sar");
-		break;
-	}
+	emulate_2op_SrcB(ctxt, "rol");
+	return X86EMUL_CONTINUE;
+}
+
+static int em_ror(struct x86_emulate_ctxt *ctxt)
+{
+	emulate_2op_SrcB(ctxt, "ror");
+	return X86EMUL_CONTINUE;
+}
+
+static int em_rcl(struct x86_emulate_ctxt *ctxt)
+{
+	emulate_2op_SrcB(ctxt, "rcl");
+	return X86EMUL_CONTINUE;
+}
+
+static int em_rcr(struct x86_emulate_ctxt *ctxt)
+{
+	emulate_2op_SrcB(ctxt, "rcr");
+	return X86EMUL_CONTINUE;
+}
+
+static int em_sal(struct x86_emulate_ctxt *ctxt)
+{
+	emulate_2op_SrcB(ctxt, "sal");
+	return X86EMUL_CONTINUE;
+}
+
+static int em_shr(struct x86_emulate_ctxt *ctxt)
+{
+	emulate_2op_SrcB(ctxt, "shr");
+	return X86EMUL_CONTINUE;
+}
+
+static int em_sar(struct x86_emulate_ctxt *ctxt)
+{
+	emulate_2op_SrcB(ctxt, "sar");
 	return X86EMUL_CONTINUE;
 }
 
@@ -3213,6 +3226,17 @@ static struct opcode group1A[] = {
 	I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N,
 };
 
+static struct opcode group2[] = {
+	I(0, em_rol),
+	I(0, em_ror),
+	I(0, em_rcl),
+	I(0, em_rcr),
+	I(0, em_sal),
+	I(0, em_shr),
+	I(0, em_sal),	/* for AMD */
+	I(0, em_sar),
+};
+
 static struct opcode group3[] = {
 	I(DstMem | SrcImm | ModRM, em_test),
 	I(DstMem | SrcImm | ModRM, em_test),
@@ -3368,7 +3392,8 @@ static struct opcode opcode_table[256] = {
 	/* 0xB8 - 0xBF */
 	X8(I(DstReg | SrcImm | Mov, em_mov)),
 	/* 0xC0 - 0xC7 */
-	D2bv(DstMem | SrcImmByte | ModRM),
+	G(DstMem | SrcImmByte | ModRM | ByteOp, group2),
+	G(DstMem | SrcImmByte | ModRM, group2),
 	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
 	I(ImplicitOps | Stack, em_ret),
 	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
@@ -3379,7 +3404,10 @@ static struct opcode opcode_table[256] = {
 	D(ImplicitOps), DI(SrcImmByte, intn),
 	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
 	/* 0xD0 - 0xD7 */
-	D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | SrcCL | ModRM),
+	G(DstMem | SrcOne | ModRM | ByteOp, group2),
+	G(DstMem | SrcOne | ModRM, group2),
+	G(DstMem | SrcCL | ModRM | ByteOp, group2),
+	G(DstMem | SrcCL | ModRM, group2),
 	N, N, N, N,
 	/* 0xD8 - 0xDF */
 	N, N, N, N, N, N, N, N,
@@ -4053,9 +4081,6 @@ special_insn:
 		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
 		}
 		break;
-	case 0xc0 ... 0xc1:
-		rc = em_grp2(ctxt);
-		break;
 	case 0xcc:		/* int3 */
 		rc = emulate_int(ctxt, 3);
 		break;
@@ -4066,12 +4091,6 @@ special_insn:
 		if (ctxt->eflags & EFLG_OF)
 			rc = emulate_int(ctxt, 4);
 		break;
-	case 0xd0 ... 0xd1:	/* Grp2 */
-		rc = em_grp2(ctxt);
-		break;
-	case 0xd2 ... 0xd3:	/* Grp2 */
-		rc = em_grp2(ctxt);
-		break;
 	case 0xe9: /* jmp rel */
 	case 0xeb: /* jmp rel short */
 		jmp_rel(ctxt, ctxt->src.val);
-- 
1.7.5.4

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