Group 2: D2, D3
ROL, ROR, RCL, RCR, SAL/SHL, SHR, SAR,
When these instructions use the CL as their source operands, the
emulator reads regs[VCPU_REGS_RCX] and then calls em_grp2().
This patch changes this to be done in the decoder by introducing
SrcCL flag like Src2CL. The only semantic change is the bit masking
which will be done in decode_operand():
op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
This reflects the descriptions in the instruction manuals better in the
sense that what it is reading is the CL.
Note: the new code was tested by adding
asm("sal %1, %0" : "+m"(*mem) : "c"((u8)3));
to kvm-unit-tests/x86/emulator.c; 0xff became 0xf8 successfully.
Signed-off-by: Takuya Yoshikawa <yoshikawa.takuya@xxxxxxxxxxxxx>
---
arch/x86/kvm/emulate.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 05a562b..2f287f4 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -101,6 +101,7 @@
#define SrcAcc (OpAcc << SrcShift)
#define SrcImmU16 (OpImmU16 << SrcShift)
#define SrcDX (OpDX << SrcShift)
+#define SrcCL (OpCL << SrcShift)
#define SrcMask (OpMask << SrcShift)
#define BitOp (1<<11)
#define MemAbs (1<<12) /* Memory operand is absolute displacement */
@@ -3378,7 +3379,7 @@ static struct opcode opcode_table[256] = {
D(ImplicitOps), DI(SrcImmByte, intn),
D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
/* 0xD0 - 0xD7 */
- D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
+ D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | SrcCL | ModRM),
N, N, N, N,
/* 0xD8 - 0xDF */
N, N, N, N, N, N, N, N,
@@ -4069,7 +4070,6 @@ special_insn:
rc = em_grp2(ctxt);
break;
case 0xd2 ... 0xd3: /* Grp2 */
- ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
rc = em_grp2(ctxt);
break;
case 0xe9: /* jmp rel */
--
1.7.5.4
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