On 12/13/2011 03:36 PM, Christoffer Dall wrote:
> > if (new_virt_intr == IRQ | FIQ && virt_intr == FIQ) {
> > /* IRQ raised, FIQ already set */
> > return;
> > }
> >
>
> hmm, so what you want to avoid here is sending an IPI to the other CPU
> in case we already have FIQ raised? But I think we have to do this
> anyhow. If a guest is servicing a raised FIQ and have FIQs masked, but
> the GIC hasn't lowered the FIQ line yet, and now comes an IRQ, if the
> IRQ is unmasked we want to change the hypervisor virtual IRQ register
> right away as to signal an IRQ immediately and if the guest masks IRQ
> we still want to change the hypervisor virtual register so that the
> moment the guest unmasks the IRQ, an exception is raised. The only way
> to set the hypervisor register for another CPU would be to have it
> take a world-switch round.
Ah, if the register is virtualized, indeed you need to signal immediately.
> >> But, if I am doing atomic bitops on an unsigned long field, how do I
> >> read that (or test two bits at once) atomically?
> >
> > Reads (and writes) are always atomic. Its read-modify-write that needs
> > special treatment.
> >
> embarrassing. I actually thought read/writes of a word could be
> partial to the byte between SMP nodes, but it turns out, and as you
> say, they cannot. Got it.
Read Documentation/atomic_ops.txt and Documentation/memory-barriers.txt,
it's a tricky subject.
--
error compiling committee.c: too many arguments to function
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