On Wed, Nov 30, 2011 at 4:59 PM, Michael S. Tsirkin <mst@xxxxxxxxxx> wrote: > I see. And this happens because the ARM processor reorders > memory writes Yes. > And in an SMP configuration, writes are somehow not reordered? They are, but then the smp memory barriers are enough to control these effects. It's not enough to control reordering as seen by a device (which is what our AMP processors are) though. (btw, the difference between an SMP processor and a device here lies in how the memory is mapped: normal memory vs. device memory attributes. it's an ARM thingy). > Just checking that this is not a bug in the smp_wmb implementation > for the specific platform. No, it's not. ARM's smp memory barriers use ARM's DMB instruction, which is enough to control SMP effects, whereas ARM's mandatory memory barriers use ARM's DSB instruction, which is required to ensure the ordering between Device and Normal memory accesses. Thanks, Ohad. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
