On Wed, Nov 30, 2011 at 01:45:05PM +0200, Ohad Ben-Cohen wrote: > > So you put virtio rings in MMIO memory? > > I'll be precise: the vrings are created in non-cacheable memory, which > both processors have access to. > > > Could you please give a couple of examples of breakage? > > Sure. Basically, the order of the vring memory operations appear > differently to the observing processor. For example, avail->idx gets > updated before the new entry is put in the available array... I see. And this happens because the ARM processor reorders memory writes to this uncacheable memory? And in an SMP configuration, writes are somehow not reordered? For example, if we had such an AMP configuration with and x86 processor, wmb() (sfence) would be wrong and smp_wmb() would be sufficient. Just checking that this is not a bug in the smp_wmb implementation for the specific platform. -- MST -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
