On Tue, Oct 18, 2011 at 01:37:32PM -0400, Avi Kivity wrote: > On 10/18/2011 06:35 PM, Roedel, Joerg wrote: > > On Tue, Oct 18, 2011 at 12:23:11PM -0400, Jan Kiszka wrote: > > > AMD processors apparently have a bug in the hardware task switching > > > support when NPT is enabled. If the task switch triggers a NPF, we can > > > get wrong EXITINTINFO along with that fault. On resume, spurious > > > exceptions may then be injected into the guest. > > > > > > We were able to reproduce this bug when our guest triggered #SS and the > > > handler were supposed to run over a separate task with not yet touched > > > stack pages. > > > > > > Work around the issue by continuing to emulate task switches even in > > > NPT mode. > > > > > > Signed-off-by: Jan Kiszka <jan.kiszka@xxxxxxxxxxx> > > > > Acked-by: Joerg Roedel <joerg.roedel@xxxxxxx> > > > > Will there be an erratum published for this bug? Are all processors > affected? > > I'd like to limit this to just the buggy processors, if and when fixed > processors become available. Actually, this isn't a bug. Please have a look at section 15.2.6 of the APM2: 15.2.6 Restartable Instructions SVM is designed to safely restart, with the exception of task switches, any intercepted instruction (either atomic or idempotent) after the intercept. So SVM does not guarantee that an intercept during a task-switch can be restarted. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo, Andrew Bowd Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
