On 10/09/2011 12:05 PM, Liu, Jinsong wrote:
Marcelo, I add test case for tsc deadline timer https://github.com/avikivity/kvm-unit-tests, as attached. According to the kvm-unit-tests README, I try to run qemu-system-x86_64 -device testdev,chardev=testlog -chardev file,id=testlog,path=apic.out -kernel ./x86/apic.flat but get nothing from the testlog 'apic.out' (BTW, at kvm side I did observe the expected tsc deadline timer action) I also try to run the README example qemu-system-x86_64 -device testdev,chardev=testlog -chardev file,id=testlog,path=msr.out -kernel ./x86/msr.flat but still get nothing from 'msr.out' Do I miss something? how can I get test log?
This was recently changed, it now outputs to the serial port. Try qemu-system-x86_64 -device testdev,chardev=testlog -chardev file,id=testlog,path=apic.out -serial stdio -kernel ./x86/apic.flat
+ +static void start_tsc_deadline_timer(void) +{ + unsigned a, d; + + handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr); + irq_enable(); + + asm ("rdmsr" : "=a"(a), "=d"(d) : "c"(MSR_IA32_TSC)); + asm ("wrmsr" : : "a"(a), "d"(d), "c"(MSR_IA32_TSCDEADLINE)); + asm volatile ("nop"); + report("tsc deadline timer", tdt_count == 1); +}
Please use rdmsr()/wrmsr() from processor.h.
+ +static int enable_tsc_deadline_timer(void) +{ + unsigned a, b, c, d; + uint32_t lvtt; + + asm ("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(1));
cpuid()...
+ + if (c& (1<< 24)) { + lvtt = TSC_DEADLINE_TIMER_MODE | TSC_DEADLINE_TIMER_VECTOR; + apic_write(APIC_LVTT, lvtt); + start_tsc_deadline_timer(); + return 1; + } else { + return 0; + } +} + +static void test_tsc_deadline_timer(void) +{ + if(enable_tsc_deadline_timer()) { + printf("tsc deadline timer enabled\n"); + } else { + printf("tsc deadline timer not detected\n"); + } +} + #define MSR_APIC_BASE 0x0000001b void test_enable_x2apic(void) @@ -291,6 +342,8 @@ int main() test_sti_nmi(); test_multiple_nmi(); + test_tsc_deadline_timer(); + printf("\nsummary: %d tests, %d failures\n", g_tests, g_fail); return g_fail != 0;
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