On Tue, Sep 13, 2011 at 04:53:18PM -0400, Don Zickus wrote: > On Tue, Sep 13, 2011 at 09:58:38PM +0200, Andi Kleen wrote: > > > Or are you saying an NMI in an idle system will have the same %rip thus > > > falsely detecting a back-to-back NMI? > > > > Yup. > > Hmm. That sucks. Is there another register that can be used in > conjunction to seperate it, like sp or something? Or we can we assume Not that I know of. > than an idle cpu isn't doing much for local NMI IPIs and that the only > NMIs that would interrupt it would be external ones? There can be still activity on the "idle" system, e.g. SMM or some Hypervisor in the background. If you profile events those might trigger samples, but they will be all accounted to the MWAIT. > > Another problem is very long running instructions, like WBINVD and some others. > > If there's a high frequency NMI it may well hit multiple times in a single > > instance. > > I thought NMIs happen on instruction boundaries, maybe not. Yes, but there may be multiple queued up when the instruction has finished executing. So you get multiple at the boundary. > Honestly, our current implementation would probably be tripped up with > those examples too, so I don't think I am making things worse (assuming > the only high frequency NMI is coming from perf). I wish perf/oprofile would just stop using NMIs. The interrupt off regions are getting smaller and smaller and they can be profiled in a limited way using PEBS anyways. Or maybe make it a knob with default to off. -Andi -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
