On Mon, Jul 25, 2011 at 04:28:12PM +0300, Avi Kivity wrote: > On 07/25/2011 04:17 PM, Gleb Natapov wrote: > >On Mon, Jul 25, 2011 at 04:14:45PM +0300, Avi Kivity wrote: > >> On 07/25/2011 04:07 PM, Anthony Liguori wrote: > >> >On 07/20/2011 11:50 AM, Avi Kivity wrote: > >> >>The current implementation of PAM and the PCI holes is broken in several > >> >>ways: > >> >> > >> >> - PCI BARs are not restricted to the PCI hole (a BAR may hide memory) > >> > > >> >Technically, a BAR can be mapped to any non-RAM memory location. > >> > >> I understood TOM (Top Of Memory) to be fixed - can't find a register > >> for it - but maybe I misread the spec. > >> > >PIIX3 spec: > > > >2.2.11. TOM—TOP OF MEMORY REGISTER (Function 0) > >Address Offset: 69h > >Default Value: 02h > >Attribute: Read/Write > > > > What's it doing in PIIX3? Is it the same TOM? > Good question. Looks like it is not: This register enables the forwarding of ISA or DMA memory cycles to the PCI Bus and sets the top of main memory accessible by ISA or DMA devices. In addition, this register controls the forwarding of ISA or DMA accesses to the lower BIOS region (E0000–EFFFFh) and the 512–640-Kbyte main memory region (80000– 9FFFFh). The Top Of Memory configuration register must be set by the BIOS. -- Gleb. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
