On Sun, Jan 30, 2011, Avi Kivity wrote about "Re: [PATCH 05/29] nVMX: Implement reading and writing of VMX MSRs":
> >+ case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
> >+ case MSR_IA32_VMX_PINBASED_CTLS:
> >+ vmx_msr_low = CORE2_PINBASED_CTLS_MUST_BE_ONE;
> >+ vmx_msr_high = CORE2_PINBASED_CTLS_MUST_BE_ONE |
> >+ PIN_BASED_EXT_INTR_MASK |
> >+ PIN_BASED_NMI_EXITING |
> >+ PIN_BASED_VIRTUAL_NMIS;
>
> Can we actually support PIN_BASED_VIRTUAL_NMIs on hosts which don't
> support them?
>
> Maybe better to drop for the initial version.
Thanks, I'll look into this. You already found this problem in June, and
it's already in my bugzilla. Just wanted to let you know that I'm taking
all your previous comments seriously, and not forgetting any of them.
Since you mention this one again, I'm increasing its priority, so I'll fix
it before the next version of the patches.
> >+static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
> >+{
> >+ if (!nested_vmx_allowed(vcpu))
> >+ return 0;
> >+
> >+ /*
> >+ * according to the spec, "VMX capability MSRs are read-only; an
> >+ * attempt to write them (with WRMSR) produces a #GP(0).
> >+ */
> >+ if (msr_index>= MSR_IA32_VMX_BASIC&&
> >+ msr_index<= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
> >+ kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
> >+ return 1;
>
> Can just drop this part, #GP is the default response.
Right, thanks, I see that now. I'll remove the extra code, but leave a
comment.
--
Nadav Har'El | Monday, Jan 31 2011, 26 Shevat 5771
nyh@xxxxxxxxxxxxxxxxxxx |-----------------------------------------
Phone +972-523-790466, ICQ 13349191 |If the universe is expanding, why can't I
http://nadav.harel.org.il |find a parking space?
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