On Sun, 12 Jan 2025 17:08:31 +0000 Marc Zyngier <maz@xxxxxxxxxx> wrote: > The ICH_MISR_EL2-related macros are missing a number of status > bits that we are about to handle. Take this opportunity to fully > describe the layout of that register as part of the automatic > generation infrastructure. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> Compared against the ARM ARM: Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx> Thanks, Andre > --- > arch/arm64/include/asm/sysreg.h | 5 ----- > arch/arm64/tools/sysreg | 12 ++++++++++++ > tools/arch/arm64/include/asm/sysreg.h | 5 ----- > 3 files changed, 12 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index cf74ebcd46d95..815e9b0bdff27 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -561,7 +561,6 @@ > > #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) > #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) > -#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) > #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) > #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) > #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) > @@ -991,10 +990,6 @@ > #define TRFCR_ELx_E0TRE BIT(0) > > /* GIC Hypervisor interface registers */ > -/* ICH_MISR_EL2 bit definitions */ > -#define ICH_MISR_EOI (1 << 0) > -#define ICH_MISR_U (1 << 1) > - > /* ICH_LR*_EL2 bit definitions */ > #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index f5927d345eea3..a601231a088d7 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -2974,6 +2974,18 @@ Res0 17:5 > Field 4:0 ListRegs > EndSysreg > > +Sysreg ICH_MISR_EL2 3 4 12 11 2 > +Res0 63:8 > +Field 7 VGrp1D > +Field 6 VGrp1E > +Field 5 VGrp0D > +Field 4 VGrp0E > +Field 3 NP > +Field 2 LRENP > +Field 1 U > +Field 0 EOI > +EndSysreg > + > Sysreg CONTEXTIDR_EL2 3 4 13 0 1 > Fields CONTEXTIDR_ELx > EndSysreg > diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h > index f43e303d31d25..0169bd3137caf 100644 > --- a/tools/arch/arm64/include/asm/sysreg.h > +++ b/tools/arch/arm64/include/asm/sysreg.h > @@ -420,7 +420,6 @@ > > #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) > #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) > -#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) > #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) > #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) > #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) > @@ -634,10 +633,6 @@ > #define TRFCR_ELx_E0TRE BIT(0) > > /* GIC Hypervisor interface registers */ > -/* ICH_MISR_EL2 bit definitions */ > -#define ICH_MISR_EOI (1 << 0) > -#define ICH_MISR_U (1 << 1) > - > /* ICH_LR*_EL2 bit definitions */ > #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) >
