On Sun, 12 Jan 2025 17:08:30 +0000
Marc Zyngier <maz@xxxxxxxxxx> wrote:
> The ICH_VTR_EL2-related macros are missing a number of config
> bits that we are about to handle. Take this opportunity to fully
> describe the layout of that register as part of the automatic
> generation infrastructure.
>
> This results in a bit of churn to repaint constants that are now
> generated with a different format.
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Compared the new definitions against the ARM ARM and can confirm that the
rest indeed just got repainted.
Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>
Cheers,
Andre
> ---
> arch/arm64/include/asm/sysreg.h | 13 -------------
> arch/arm64/kvm/vgic-sys-reg-v3.c | 8 ++++----
> arch/arm64/kvm/vgic/vgic-v3.c | 16 +++++++---------
> arch/arm64/tools/sysreg | 14 ++++++++++++++
> tools/arch/arm64/include/asm/sysreg.h | 13 -------------
> 5 files changed, 25 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 3e84ef8f5b311..cf74ebcd46d95 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -561,7 +561,6 @@
>
> #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
> #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
> -#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
> #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
> #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
> #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
> @@ -1030,18 +1029,6 @@
> #define ICH_VMCR_ENG1_SHIFT 1
> #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
>
> -/* ICH_VTR_EL2 bit definitions */
> -#define ICH_VTR_PRI_BITS_SHIFT 29
> -#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
> -#define ICH_VTR_ID_BITS_SHIFT 23
> -#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
> -#define ICH_VTR_SEIS_SHIFT 22
> -#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
> -#define ICH_VTR_A3V_SHIFT 21
> -#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
> -#define ICH_VTR_TDS_SHIFT 19
> -#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
> -
> /*
> * Permission Indirection Extension (PIE) permission encodings.
> * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
> diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c
> index 9e7c486b48c2e..5eacb4b3250a1 100644
> --- a/arch/arm64/kvm/vgic-sys-reg-v3.c
> +++ b/arch/arm64/kvm/vgic-sys-reg-v3.c
> @@ -35,12 +35,12 @@ static int set_gic_ctlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
>
> vgic_v3_cpu->num_id_bits = host_id_bits;
>
> - host_seis = FIELD_GET(ICH_VTR_SEIS_MASK, kvm_vgic_global_state.ich_vtr_el2);
> + host_seis = FIELD_GET(ICH_VTR_EL2_SEIS, kvm_vgic_global_state.ich_vtr_el2);
> seis = FIELD_GET(ICC_CTLR_EL1_SEIS_MASK, val);
> if (host_seis != seis)
> return -EINVAL;
>
> - host_a3v = FIELD_GET(ICH_VTR_A3V_MASK, kvm_vgic_global_state.ich_vtr_el2);
> + host_a3v = FIELD_GET(ICH_VTR_EL2_A3V, kvm_vgic_global_state.ich_vtr_el2);
> a3v = FIELD_GET(ICC_CTLR_EL1_A3V_MASK, val);
> if (host_a3v != a3v)
> return -EINVAL;
> @@ -68,10 +68,10 @@ static int get_gic_ctlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
> val |= FIELD_PREP(ICC_CTLR_EL1_PRI_BITS_MASK, vgic_v3_cpu->num_pri_bits - 1);
> val |= FIELD_PREP(ICC_CTLR_EL1_ID_BITS_MASK, vgic_v3_cpu->num_id_bits);
> val |= FIELD_PREP(ICC_CTLR_EL1_SEIS_MASK,
> - FIELD_GET(ICH_VTR_SEIS_MASK,
> + FIELD_GET(ICH_VTR_EL2_SEIS,
> kvm_vgic_global_state.ich_vtr_el2));
> val |= FIELD_PREP(ICC_CTLR_EL1_A3V_MASK,
> - FIELD_GET(ICH_VTR_A3V_MASK, kvm_vgic_global_state.ich_vtr_el2));
> + FIELD_GET(ICH_VTR_EL2_A3V, kvm_vgic_global_state.ich_vtr_el2));
> /*
> * The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
> * Extract it directly using ICC_CTLR_EL1 reg definitions.
> diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
> index 6c21be12959d6..0bdecbbe74898 100644
> --- a/arch/arm64/kvm/vgic/vgic-v3.c
> +++ b/arch/arm64/kvm/vgic/vgic-v3.c
> @@ -283,12 +283,10 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
> vgic_v3->vgic_sre = 0;
> }
>
> - vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
> - ICH_VTR_ID_BITS_MASK) >>
> - ICH_VTR_ID_BITS_SHIFT;
> - vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
> - ICH_VTR_PRI_BITS_MASK) >>
> - ICH_VTR_PRI_BITS_SHIFT) + 1;
> + vcpu->arch.vgic_cpu.num_id_bits = FIELD_GET(ICH_VTR_EL2_IDbits,
> + kvm_vgic_global_state.ich_vtr_el2);
> + vcpu->arch.vgic_cpu.num_pri_bits = FIELD_GET(ICH_VTR_EL2_PRIbits,
> + kvm_vgic_global_state.ich_vtr_el2) + 1;
>
> /* Get the show on the road... */
> vgic_v3->vgic_hcr = ICH_HCR_EL2_En;
> @@ -632,7 +630,7 @@ static const struct midr_range broken_seis[] = {
>
> static bool vgic_v3_broken_seis(void)
> {
> - return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&
> + return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_EL2_SEIS) &&
> is_midr_in_range_list(read_cpuid_id(), broken_seis));
> }
>
> @@ -706,10 +704,10 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
> if (vgic_v3_broken_seis()) {
> kvm_info("GICv3 with broken locally generated SEI\n");
>
> - kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
> + kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_EL2_SEIS;
> group0_trap = true;
> group1_trap = true;
> - if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
> + if (ich_vtr_el2 & ICH_VTR_EL2_TDS)
> dir_trap = true;
> else
> common_trap = true;
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 9938926421b5c..f5927d345eea3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2960,6 +2960,20 @@ Field 1 UIE
> Field 0 En
> EndSysreg
>
> +Sysreg ICH_VTR_EL2 3 4 12 11 1
> +Res0 63:32
> +Field 31:29 PRIbits
> +Field 28:26 PREbits
> +Field 25:23 IDbits
> +Field 22 SEIS
> +Field 21 A3V
> +Field 20 nV4
> +Field 19 TDS
> +Field 18 DVIM
> +Res0 17:5
> +Field 4:0 ListRegs
> +EndSysreg
> +
> Sysreg CONTEXTIDR_EL2 3 4 13 0 1
> Fields CONTEXTIDR_ELx
> EndSysreg
> diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
> index d314ccab7560a..f43e303d31d25 100644
> --- a/tools/arch/arm64/include/asm/sysreg.h
> +++ b/tools/arch/arm64/include/asm/sysreg.h
> @@ -420,7 +420,6 @@
>
> #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
> #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
> -#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
> #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
> #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
> #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
> @@ -673,18 +672,6 @@
> #define ICH_VMCR_ENG1_SHIFT 1
> #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
>
> -/* ICH_VTR_EL2 bit definitions */
> -#define ICH_VTR_PRI_BITS_SHIFT 29
> -#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
> -#define ICH_VTR_ID_BITS_SHIFT 23
> -#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
> -#define ICH_VTR_SEIS_SHIFT 22
> -#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
> -#define ICH_VTR_A3V_SHIFT 21
> -#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
> -#define ICH_VTR_TDS_SHIFT 19
> -#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
> -
> /*
> * Permission Indirection Extension (PIE) permission encodings.
> * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
