[AMD Official Use Only - AMD Internal Distribution Only] > -----Original Message----- > From: Josh Poimboeuf <jpoimboe@xxxxxxxxxx> > Sent: Thursday, November 14, 2024 11:49 PM > To: Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx> > Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>; Amit Shah > <amit@xxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx; kvm@xxxxxxxxxxxxxxx; > x86@xxxxxxxxxx; linux-doc@xxxxxxxxxxxxxxx; Shah, Amit > <Amit.Shah@xxxxxxx>; Lendacky, Thomas <Thomas.Lendacky@xxxxxxx>; > bp@xxxxxxxxx; tglx@xxxxxxxxxxxxx; peterz@xxxxxxxxxxxxx; corbet@xxxxxxx; > mingo@xxxxxxxxxx; dave.hansen@xxxxxxxxxxxxxxx; hpa@xxxxxxxxx; > seanjc@xxxxxxxxxx; pbonzini@xxxxxxxxxx; > daniel.sneddon@xxxxxxxxxxxxxxx; kai.huang@xxxxxxxxx; Das1, Sandipan > <Sandipan.Das@xxxxxxx>; boris.ostrovsky@xxxxxxxxxx; Moger, Babu > <Babu.Moger@xxxxxxx>; Kaplan, David <David.Kaplan@xxxxxxx>; > dwmw@xxxxxxxxxxxx > Subject: Re: [RFC PATCH v2 1/3] x86: cpu/bugs: update SpectreRSB comments > for AMD > > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. > > > On Thu, Nov 14, 2024 at 12:01:16AM -0800, Pawan Gupta wrote: > > > For PBRSB, I guess we don't need to worry about that since there > > > would be at least one kernel CALL before context switch. > > > > Right. So the case where we need RSB filling at context switch is > > retpoline+CDT mitigation. > > According to the docs, classic IBRS also needs RSB filling at context switch to > protect against corrupt RSB entries (as opposed to RSB underflow). Which docs are that? Classic IBRS doesn't do anything with returns (at least on AMD). The AMD docs say that if you want to prevent earlier instructions from influencing later RETs, you need to do the 32 CALL sequence. But I'm not sure what corrupt RSB entries mean here, and how it relates to IBRS? --David Kaplan
