Hi Sandipan, On 11/6/24 1:58 AM, Sandipan Das wrote: [snip] >> @@ -4830,6 +4966,20 @@ static int kvm_get_msrs(X86CPU *cpu) >> case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: >> env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; >> break; >> + case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL0 + 3: > > The upper bound is very unlikely to change but rewriting MSR_K7_EVNTSEL0 + 3 as > MSR_K7_EVNTSEL0 + AMD64_NUM_COUNTERS - 1 may be more readable. Same applies to > MSR_K7_PERFCTR below. > >> + env->msr_gp_evtsel[index - MSR_K7_EVNTSEL0] = msrs[i].data; >> + break; >> + case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR0 + 3: >> + env->msr_gp_counters[index - MSR_K7_PERFCTR0] = msrs[i].data; >> + break; >> + case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTL0 + 0xb: > > Same as above except this one needs AMD64_NUM_COUNTERS_CORE * 2 - 1. Unlike the AMD PMU K7, I assume it is more likely the number of counters may be changed in the future (so far it is still 6 on my test server with PerfMonV2). I will make it more readable in v2 following your suggestion. Thank you very much! Dongli Zhang
