On Fri, Oct 18, 2024 at 08:58:03AM +0100, Daniel P. Berrangé wrote: > Date: Fri, 18 Oct 2024 08:58:03 +0100 > From: "Daniel P. Berrangé" <berrange@xxxxxxxxxx> > Subject: Re: [PATCH v3 6/7] i386/pc: Support cache topology in -machine for > PC machine > > On Fri, Oct 18, 2024 at 11:57:36AM +0800, Zhao Liu wrote: > > Hi Daniel, > > > > > > + ``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel`` > > > > + Define cache properties for SMP system. > > > > + > > > > + ``cache=cachename`` specifies the cache that the properties will be > > > > + applied on. This field is the combination of cache level and cache > > > > + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction > > > > + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). > > > > + > > > > + ``topology=topologylevel`` sets the cache topology level. It accepts > > > > + CPU topology levels including ``thread``, ``core``, ``module``, > > > > + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a special > > > > + value ``default``. If ``default`` is set, then the cache topology will > > > > + follow the architecture's default cache topology model. If another > > > > + topology level is set, the cache will be shared at corresponding CPU > > > > + topology level. For example, ``topology=core`` makes the cache shared > > > > + by all threads within a core. > > > > + > > > > + Example: > > > > + > > > > + :: > > > > + > > > > + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core > > > > > > There are 4 cache types, l1d, l1i, l2, l3. > > > > > > In this example you've only set properties for l1d, l1i caches. > > > > > > What does this mean for l2 / l3 caches ? > > > > Omitting "cache" will default to using the "default" level. > > > > I think I should add the above description to the documentation. > > > > > Are they reported as not existing, or are they to be reported at > > > some built-in default topology level. > > > > It's the latter. > > > > If a machine doesn't support l2/l3, then QEMU will also report the error > > like: > > > > qemu-system-*: l2 cache topology not supported by this machine > > Ok, that's good. > > > > If the latter, how does the user know what that built-in default is, > > > > Currently, the default cache model for x86 is L1 per core, L2 per core, > > and L3 per die. Similar to the topology levels, there is still no way to > > expose this to users. I can descript default cache model in doc. > > > > But I feel like we're back to the situation we discussed earlier: > > "default" CPU topology support should be related to the CPU model, but > > in practice, QEMU supports it at the machine level. The cache topology > > depends on CPU topology support and can only continue to be added on top > > of the machine. > > > > So do you think we can add topology and cache information in CpuModelInfo > > so that query-cpu-model-expansion can expose default CPU/cache topology > > information to users? > > > > This way, users can customize CPU/cache topology in -smp and > > -machine smp-cache. Although the QMP command is targeted at the CPU model > > while our CLI is at the machine level, at least we can expose the > > information to users. > > > > If you agree to expose the default topology/cache info in > > query-cpu-model-expansion, can I work on this in a separate series? :) > > Yeah, lets worry about that another day. > > It it sufficient to just encourage users to always specify > the full set of caches. Thanks! > > > Can we explicitly disable a l2/l3 cache, or must it always exists ? > > > > Now we can't disable it through -machine smp-cache (while x86 CPU support > > l3-cache=off), but as you mentioned, I can try using "invalid" to support > > this scenario, which would be more general. Similarly, if you agree, I > > can also add this support in a separate series. > > If we decide to offer a way to disable caches, probably better to have > a name like 'disabled' for such a setting, and yes, we don't need todo > that now. Yes, "disabled" is better. Regards, Zhao
