On Sat, Oct 12, 2024 at 06:44:28PM +0800, Zhao Liu wrote: > Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC > machine. > > Additionally, add the document of "-machine smp-cache" in > qemu-options.hx. > > Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx> > Tested-by: Yongwei Ma <yongwei.ma@xxxxxxxxx> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> > --- > Changes since Patch v2: > * Polished the document. (Jonathan) > > Changes since Patch v1: > * Merged document into this patch. (Markus) > > Changes since RFC v2: > * Used cache_supported array. > --- > hw/i386/pc.c | 4 ++++ > qemu-options.hx | 26 +++++++++++++++++++++++++- > 2 files changed, 29 insertions(+), 1 deletion(-) > > -machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512 > + > + ``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel`` > + Define cache properties for SMP system. > + > + ``cache=cachename`` specifies the cache that the properties will be > + applied on. This field is the combination of cache level and cache > + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction > + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). > + > + ``topology=topologylevel`` sets the cache topology level. It accepts > + CPU topology levels including ``thread``, ``core``, ``module``, > + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a special > + value ``default``. If ``default`` is set, then the cache topology will > + follow the architecture's default cache topology model. If another > + topology level is set, the cache will be shared at corresponding CPU > + topology level. For example, ``topology=core`` makes the cache shared > + by all threads within a core. > + > + Example: > + > + :: > + > + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core There are 4 cache types, l1d, l1i, l2, l3. In this example you've only set properties for l1d, l1i caches. What does this mean for l2 / l3 caches ? Are they reported as not existing, or are they to be reported at some built-in default topology level. If the latter, how does the user know what that built-in default is, and avoid nonsense like l1d being at socket level, and l3 being at the core level ? Can we explicitly disable a l2/l3 cache, or must it always exists ? The QAPI has an "invalid" topology level. You've not documented that as permitted here, but the qapi parser will happily allow it. What semantics will that have ? With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|