On Mon, Oct 7, 2024 at 7:30 AM Borislav Petkov <bp@xxxxxxxxx> wrote: > > On Fri, Sep 13, 2024 at 10:32:27AM -0700, Jim Mattson wrote: > > AMD's initial implementation of IBPB did not clear the return address > > predictor. Beginning with Zen4, AMD's IBPB *does* clear the return > > address predictor. This behavior is enumerated by > > CPUID.80000008H:EBX.IBPB_RET[bit 30]. > > > > Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, > > when determining cross-vendor capabilities. > > > > Suggested-by: Venkatesh Srinivas <venkateshs@xxxxxxxxxxxx> > > Signed-off-by: Jim Mattson <jmattson@xxxxxxxxxx> > > --- > > arch/x86/include/asm/cpufeatures.h | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index cabd6b58e8ec..a222a24677d7 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -215,7 +215,7 @@ > > #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */ > > #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */ > > #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */ > > -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without RSB flush */ > > I see upstream > > #define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */ > > Where does "without RSB flush" come from? Bad git hygiene. This should have been a 4 patch set, not a 3 patch set. Sigh. I'll send out v5.
