On Fri, Sep 27, 2024 at 06:51:58AM -0700, Sean Christopherson wrote: > On Thu, Sep 26, 2024, Yan Zhao wrote: > > On Thu, Sep 12, 2024 at 05:07:57PM -0700, Sean Christopherson wrote: > > > > diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h > > > > index a72f0e3bde17..1726f8ec5a50 100644 > > > > --- a/arch/x86/kvm/mmu/spte.h > > > > +++ b/arch/x86/kvm/mmu/spte.h > > > > @@ -214,6 +214,12 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask; > > > > */ > > > > #define FROZEN_SPTE (SHADOW_NONPRESENT_VALUE | 0x5a0ULL) > > > > > > > > +#define EXTERNAL_SPTE_IGNORE_CHANGE_MASK \ > > > > + (shadow_acc_track_mask | \ > > > > + (SHADOW_ACC_TRACK_SAVED_BITS_MASK << \ > > > > + SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) | \ > > > > > > Just make TDX require A/D bits, there's no reason to care about access tracking. > > If KVM_PRE_FAULT_MEMORY is allowed for TDX and if > > cpu_has_vmx_ept_ad_bits() is false in TDX's hardware (not sure if it's possible), > > Make it a requirement in KVM that TDX hardware supports A/D bits and that KVM's > module param is enabled. EPT A/D bits have been supported in all CPUs since > Haswell, I don't expect them to ever go away. Got it! > > > access tracking bit is possbile to be changed, as in below scenario: > > > > 1. KVM_PRE_FAULT_MEMORY ioctl calls kvm_arch_vcpu_pre_fault_memory() to map > > a GFN, and make_spte() will call mark_spte_for_access_track() to > > remove shadow_acc_track_mask (i.e. RWX bits) and move R+X left to > > SHADOW_ACC_TRACK_SAVED_BITS_SHIFT. > > 2. If a concurrent page fault occurs on the same GFN on another vCPU, then > > make_spte() in that vCPU will not see prefetch and the new_spte is > > with RWX bits and with no bits set in SHADOW_ACC_TRACK_SAVED_MASK. > > This should be fixed by the mega-series. I'll make sure to Cc you on that series. Thanks! > Thanks much for the input and feedback! :)
