> -----Original Message-----
> From: Oliver Upton <oliver.upton@xxxxxxxxx>
> Sent: Monday, September 9, 2024 5:57 PM
> To: Marc Zyngier <maz@xxxxxxxxxx>
> Cc: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@xxxxxxxxxx>;
> kvmarm@xxxxxxxxxxxxxxx; Sebastian Ott <sebott@xxxxxxxxxx>; James Morse
> <james.morse@xxxxxxx>; Suzuki K Poulose <suzuki.poulose@xxxxxxx>;
> yuzenghui <yuzenghui@xxxxxxxxxx>; kvm@xxxxxxxxxxxxxxx; Shaoqin Huang
> <shahuang@xxxxxxxxxx>; Eric Auger <eric.auger@xxxxxxxxxx>; Wangzhou
> (B) <wangzhou1@xxxxxxxxxxxxx>
> Subject: Re: [PATCH v5 07/10] KVM: arm64: Treat CTR_EL0 as a VM feature ID
> register
>
> On Mon, Sep 09, 2024 at 05:28:48PM +0100, Marc Zyngier wrote:
> > Hi Shameer,
> >
> > On Mon, 09 Sep 2024 16:19:54 +0100,
> > Shameerali Kolothum Thodi <shameerali.kolothum.thodi@xxxxxxxxxx>
> wrote:
> > >
> > > Hi Oliver/Sebastian,
> > >
> > > > -----Original Message-----
> > > > From: Oliver Upton <oliver.upton@xxxxxxxxx>
> > > > Sent: Wednesday, June 19, 2024 6:41 PM
> > > > To: kvmarm@xxxxxxxxxxxxxxx
> > > > Cc: Marc Zyngier <maz@xxxxxxxxxx>; James Morse
> > > > <james.morse@xxxxxxx>; Suzuki K Poulose
> <suzuki.poulose@xxxxxxx>;
> > > > yuzenghui <yuzenghui@xxxxxxxxxx>; kvm@xxxxxxxxxxxxxxx; Sebastian
> > > > Ott <sebott@xxxxxxxxxx>; Shaoqin Huang <shahuang@xxxxxxxxxx>;
> Eric
> > > > Auger <eric.auger@xxxxxxxxxx>; Oliver Upton
> > > > <oliver.upton@xxxxxxxxx>
> > > > Subject: [PATCH v5 07/10] KVM: arm64: Treat CTR_EL0 as a VM
> > > > feature ID register
> > >
> > > [...]
> > >
> > > > @@ -2487,7 +2490,10 @@ static const struct sys_reg_desc
> > > > sys_reg_descs[] = {
> > > > { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
> > > > { SYS_DESC(SYS_SMIDR_EL1), undef_access },
> > > > { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown,
> > > > CSSELR_EL1 },
> > > > - { SYS_DESC(SYS_CTR_EL0), access_ctr },
> > > > + ID_WRITABLE(CTR_EL0, CTR_EL0_DIC_MASK |
> > > > + CTR_EL0_IDC_MASK |
> > > > + CTR_EL0_DminLine_MASK |
> > > > + CTR_EL0_IminLine_MASK),
> > >
> > > (Sorry if this was discussed earlier, but I couldn't locate it
> > > anywhere.)
> > >
> > > Is there a reason why we can't make the L1Ip writable as well here?
> > > We do have hardware that reports VIPT and PIPT for L11p.
> > >
> > > The comment here states,
> > > https://elixir.bootlin.com/linux/v6.11-rc7/source/arch/arm64/kernel/
> > > cpufeature.c#L489
> > >
> > > " If we have differing I-cache policies, report it as the weakest - VIPT."
> > >
> > > Does this also mean it is safe to downgrade the PIPT to VIPT for Guest as
> well?
> >
> > It should be safe, as a PIPT CMO always does at least the same as
> > VIPT, and potentially more if there is aliasing.
>
> +1, there was no particular reason why this wasn't handled before.
>
> We should be careful to only allow userspace to select VIPT or PIPT (where
> permissible), and not necessarily any value lower than what's reported by
> hardware.
VIPT 0b10
PIPT 0b11
Ok. Just to clarify that " not necessarily any value lower than what's reported by
hardware" means userspace can set PIPT if hardware supports VIPT?
Based on this,
" If we have differing I-cache policies, report it as the weakest - VIPT." , I was thinking
the other way around(see "safe to downgrade PIPT to VIPT"). But Marc also
seems to suggest PIPT CMO ends up doing atleast same as VIPT and more, so it looks like
the other way. If that's the case, what does that "report it as the weakest" means for host?
(I will send out a patch, once the above is clarified)
Thanks,
Shameer
