On Thu, Aug 22, 2024, Tom Lendacky wrote: > On 8/22/24 14:41, Sean Christopherson wrote: > > On Thu, Aug 22, 2024, Tom Lendacky wrote: > >> On 8/22/24 13:44, Sean Christopherson wrote: > >>> +Tom > >>> > >>> Can someone from AMD confirm that this is indeed the behavior, and that for AMD > >>> CPUs, it's the architectural behavior? > >> > >> In section "16.11 Accessing x2APIC Register" of APM Vol 2, there is this > >> statement: > >> > >> "For 64-bit x2APIC registers, the high-order bits (bits 63:32) are > >> mapped to EDX[31:0]" > >> > >> and in section "16.11.1 x2APIC Register Address Space" of APM Vol 2, > >> there is this statement: > >> > >> "The two 32-bit Interrupt Command Registers in APIC mode (MMIO offsets > >> 300h and 310h) are merged into a single 64-bit x2APIC register at MSR > >> address 830h." > >> > >> So I believe this isn't necessary. @Suravee, agree? > >> > >> Are you seeing a bug related to this? > > > > Yep. With APICv and x2APIC enabled, Intel CPUs use a single 64-bit value at > > offset 300h for the backing storage. This is what KVM currently implements, > > e.g. when pulling state out of the vAPIC page for migration, and when emulating > > a RDMSR(ICR). > > > > With AVIC and x2APIC (a.k.a. x2AVIC enabled), Genoa uses the legacy MMIO offsets > > for storage, at least AFAICT. I.e. the single MSR at 830h is split into separate > > 32-bit values at 300h and 310h on WRMSR, and then reconstituted on RDMSR. > > > > The APM doesn't actually clarify the layout of the backing storage, i.e. doesn't > > explicitly say that the full 64-bit value is stored at 300h. IIRC, Intel's SDM > > Ah, for x2AVIC, yes, you have to do two writes to the backing page. One > at offset 0x300 and one at offset 0x310 (confirmed with the hardware > team). The order shouldn't matter since the guest vCPU isn't running > when you're writing the values, but you should do the IRC High write > first, followed by the ICR Low. Thanks Tom!
