I made the mistake of expanding my testing to run with and without AVIC
enabled, and to my surprise (wow, sarcasm), x2AVIC failed hard on the
xapic_state_test due to ICR issues.
AFAICT, the issue is that AMD splits the 64-bit ICR into the legacy ICR
and ICR2 fields when storing the ICR in the vAPIC (apparently "it's a
single 64-bit register" is open to intepretation). Aside from causing
the selftest failure and potential live migration issues, botching the
format is quite bad, as KVM will mishandle incomplete virtualized IPIs,
e.g. generate IRQs to the wrong vCPU, drop IRQs, etc.
Patch 1 fixes are rather annoying wart where the xapic_state *deliberately*
skips reserved bit tests to work around a KVM bug. *sigh*
I couldn't find anything definitive in the APM, my findings are based on
testing on Genoa.
v2: Actually send the whole series.
Sean Christopherson (10):
KVM: x86: Enforce x2APIC's must-be-zero reserved ICR bits
KVM: x86: Move x2APIC ICR helper above kvm_apic_write_nodecode()
KVM: x86: Re-split x2APIC ICR into ICR+ICR2 for AMD (x2AVIC)
KVM: selftests: Open code vcpu_run() equivalent in guest_printf test
KVM: selftests: Report unhandled exceptions on x86 as regular guest
asserts
KVM: selftests: Add x86 helpers to play nice with x2APIC MSR #GPs
KVM: selftests: Skip ICR.BUSY test in xapic_state_test if x2APIC is
enabled
KVM: selftests: Test x2APIC ICR reserved bits
KVM: selftests: Verify the guest can read back the x2APIC ICR it wrote
KVM: selftests: Play nice with AMD's AVIC errata
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/kvm/lapic.c | 73 +++++++++++++------
arch/x86/kvm/svm/svm.c | 2 +
arch/x86/kvm/vmx/main.c | 2 +
.../testing/selftests/kvm/guest_print_test.c | 19 ++++-
.../selftests/kvm/include/x86_64/apic.h | 21 +++++-
.../selftests/kvm/lib/x86_64/processor.c | 8 +-
.../selftests/kvm/x86_64/xapic_state_test.c | 54 +++++++++-----
8 files changed, 135 insertions(+), 46 deletions(-)
base-commit: 332d2c1d713e232e163386c35a3ba0c1b90df83f
--
2.45.2.1089.g2a221341d9-goog
