On Tue, Aug 06, 2024 at 07:19:18AM +0000, Tian, Kevin wrote: > " > Bit 3 should be set to 1b if the data is prefetchable and set to 0b > otherwise. A Function is permitted to mark a range as prefetchable > if there are no side effects on reads, the Function returns all bytes > on reads regardless of the byte enables, and host bridges can > merge processor writes into this range without causing errors. > " > > Above kind of suggests that using WC on a non-prefetchable BAR > may cause errors then "prefetch and WC are related" does make > some sense? prefetch exists in the spec to support historical old pre-PCI-x environments where a bridge does all kinds of strange things. prefetch turns that brdige behavior on because otherwise it is non backwards compatible. In a modern PCIe environment the fabric is perfectly TLP preserving and the PCI spec concept if prefetch is entirely vestigial. There is no clean mapping of what PCI spec prefetch contemplates with how moderns CPUs actually work. They should never be comingled. Today we expect the driver to understand what TLPs the CPU should emit and do the correct thing. From a Linux programming model with modern HW we never really permit "merge process writes" or expect "speculative reads" on anything except explicit WC mappings. Jason
