> From: Jason Gunthorpe <jgg@xxxxxxxx> > Sent: Friday, August 2, 2024 10:33 PM > > On Fri, Aug 02, 2024 at 08:24:49AM -0600, Keith Busch wrote: > > On Thu, Aug 01, 2024 at 11:33:44AM -0600, Alex Williamson wrote: > > > On Thu, 1 Aug 2024 14:13:55 -0300 > > > Jason Gunthorpe <jgg@xxxxxxxx> wrote: > > > > > > > On Thu, Aug 01, 2024 at 10:52:18AM -0600, Alex Williamson wrote: > > > > > > > > We'd populate these new regions only for BARs that support prefetch > and > > > > > mmap > > > > > > > > That's not the point, prefetch has nothing to do with write combining. > > > > > > I was following the original proposal in this thread that added a > > > prefetch flag to REGION_INFO and allowed enabling WC only for > > > IORESOURCE_PREFETCH. > > > > Which itself follows the existing pattern from > > pci_create_resource_files(), which creates a write combine > > resource<X>_wc file only when IORESOURCE_PREFETCH is set. But yeah, > > prefetch isn't necessary for wc, but it seems to indicate it's safe. > > Yes, I know, that code isn't right either... It seems to be the root > of this odd "prefetch and WC are related" idea. > According to PCIe spec: " Bit 3 should be set to 1b if the data is prefetchable and set to 0b otherwise. A Function is permitted to mark a range as prefetchable if there are no side effects on reads, the Function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. " Above kind of suggests that using WC on a non-prefetchable BAR may cause errors then "prefetch and WC are related" does make some sense?
