On Tue, Jun 04, 2024 at 10:54:51AM +0200, Markus Armbruster wrote: > Zhao Liu <zhao1.liu@xxxxxxxxx> writes: > > > Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in > > -smp to define the cache topology for SMP system. > > > > Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx> > > [...] > > > diff --git a/qapi/machine.json b/qapi/machine.json > > index 7ac5a05bb9c9..8fa5af69b1bf 100644 > > --- a/qapi/machine.json > > +++ b/qapi/machine.json > > @@ -1746,6 +1746,23 @@ > > # > > # @threads: number of threads per core > > # > > +# @l1d-cache: topology hierarchy of L1 data cache. It accepts the CPU > > +# topology enumeration as the parameter, i.e., CPUs in the same > > +# topology container share the same L1 data cache. (since 9.1) > > +# > > +# @l1i-cache: topology hierarchy of L1 instruction cache. It accepts > > +# the CPU topology enumeration as the parameter, i.e., CPUs in the > > +# same topology container share the same L1 instruction cache. > > +# (since 9.1) > > +# > > +# @l2-cache: topology hierarchy of L2 unified cache. It accepts the CPU > > +# topology enumeration as the parameter, i.e., CPUs in the same > > +# topology container share the same L2 unified cache. (since 9.1) > > +# > > +# @l3-cache: topology hierarchy of L3 unified cache. It accepts the CPU > > +# topology enumeration as the parameter, i.e., CPUs in the same > > +# topology container share the same L3 unified cache. (since 9.1) > > +# > > # Since: 6.1 > > ## > > The new members are all optional. What does "absent" mean? No such > cache? Some default topology? > > Is this sufficiently general? Do all machines of interest have a split > level 1 cache, a level 2 cache, and a level 3 cache? Level 4 cache is apparently a thing https://www.guru3d.com/story/intel-confirms-l4-cache-in-upcoming-meteor-lake-cpus/ but given that any new cache levels will require new code in QEMU to wire up, its not a big deal to add new properties at the same time. That said see my reply just now to the cover letter, where I suggest we should have a "caches" property that takes an array of cache info objects. > > Is the CPU topology level the only cache property we'll want to > configure here? If the answer isn't "yes", then we should perhaps wrap > it in an object, so we can easily add more members later. Cache size is a piece of info I could see us wanting to express > Two spaces between sentences for consistency, please. > > > { 'struct': 'SMPConfiguration', 'data': { > > @@ -1758,7 +1775,11 @@ > > '*modules': 'int', > > '*cores': 'int', > > '*threads': 'int', > > - '*maxcpus': 'int' } } > > + '*maxcpus': 'int', > > + '*l1d-cache': 'CPUTopoLevel', > > + '*l1i-cache': 'CPUTopoLevel', > > + '*l2-cache': 'CPUTopoLevel', > > + '*l3-cache': 'CPUTopoLevel' } } > > > > ## > > # @x-query-irq: > > diff --git a/system/vl.c b/system/vl.c > > [...] > With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
