Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in
-smp to define the cache topology for SMP system.
Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx>
---
Changes since RFC v1:
* Set has_*_cache field in machine_get_smp(). (JeeHeng)
* Adjust string breaking style in error_setg() for more semantic
sentence breaking conventions. (Jonathan)
* Add more description about cache options. (Markus)
* Now in v2, config->*_cache field stores topology enumeration instead
of string, no need to parse, so just make machine_check_cache_topo()
return boolean.
---
hw/core/machine-smp.c | 146 +++++++++++++++++++++++++++++++++++++++++
hw/core/machine.c | 20 ++++++
qapi/machine.json | 23 ++++++-
system/vl.c | 12 ++++
tests/unit/meson.build | 3 +-
5 files changed, 202 insertions(+), 2 deletions(-)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 5d8d7edcbd3f..c79464cf3d2c 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -61,6 +61,150 @@ static char *cpu_hierarchy_to_string(MachineState *ms)
return g_string_free(s, false);
}
+static bool machine_check_topo_support(MachineState *ms,
+ CPUTopoLevel topo)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ if (topo == CPU_TOPO_LEVEL_MODULE && !mc->smp_props.modules_supported) {
+ return false;
+ }
+
+ if (topo == CPU_TOPO_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) {
+ return false;
+ }
+
+ if (topo == CPU_TOPO_LEVEL_DIE && !mc->smp_props.dies_supported) {
+ return false;
+ }
+
+ if (topo == CPU_TOPO_LEVEL_BOOK && !mc->smp_props.books_supported) {
+ return false;
+ }
+
+ if (topo == CPU_TOPO_LEVEL_DRAWER && !mc->smp_props.drawers_supported) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool machine_check_cache_topo(MachineState *ms,
+ CPUTopoLevel topo,
+ Error **errp)
+{
+ if (topo == CPU_TOPO_LEVEL__MAX || topo == CPU_TOPO_LEVEL_INVALID) {
+ error_setg(errp,
+ "Invalid cache topology level: %s. "
+ "The cache topology should match the "
+ "valid CPU topology level",
+ cpu_topo_to_string(topo));
+ return false;
+ }
+
+ if (!machine_check_topo_support(ms, topo)) {
+ error_setg(errp,
+ "Invalid cache topology level: %s. "
+ "The topology level is not supported by this machine",
+ cpu_topo_to_string(topo));
+ return false;
+ }
+
+ return true;
+}
+
+static void machine_parse_smp_cache_config(MachineState *ms,
+ const SMPConfiguration *config,
+ Error **errp)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ /*
+ * The cache topology does not support a default entry similar to
+ * CPU topology with parameters=1. So when the machine explicitly
+ * does not support cache topology, return the error.
+ */
+ if (config->has_l1d_cache) {
+ if (!mc->smp_props.l1_separated_cache_supported) {
+ error_setg(errp,
+ "L1 D-cache topology not supported by this machine");
+ return;
+ }
+
+ if (!machine_check_cache_topo(ms, config->l1d_cache, errp)) {
+ return;
+ }
+
+ ms->smp_cache.l1d = config->l1d_cache;
+ }
+
+ if (config->has_l1i_cache) {
+ if (!mc->smp_props.l1_separated_cache_supported) {
+ error_setg(errp,
+ "L1 I-cache topology not supported by this machine");
+ return;
+ }
+
+ if (!machine_check_cache_topo(ms, config->l1i_cache, errp)) {
+ return;
+ }
+
+ ms->smp_cache.l1i = config->l1i_cache;
+ }
+
+ if (config->has_l2_cache) {
+ if (!mc->smp_props.l2_unified_cache_supported) {
+ error_setg(errp,
+ "L2 cache topology not supported by this machine");
+ return;
+ }
+
+ if (!machine_check_cache_topo(ms, config->l2_cache, errp)) {
+ return;
+ }
+
+ ms->smp_cache.l2 = config->l2_cache;
+
+ /*
+ * Cache topology is initialized by default to CPU_TOPO_LEVEL_INVALID,
+ * which is the lowest level, so such a check is OK, even if the config
+ * doesn't override that field.
+ */
+ if (ms->smp_cache.l1d > ms->smp_cache.l2 ||
+ ms->smp_cache.l1i > ms->smp_cache.l2) {
+ error_setg(errp,
+ "Invalid L2 cache topology. "
+ "L2 cache topology level should not be lower than "
+ "L1 D-cache/L1 I-cache");
+ return;
+ }
+ }
+
+ if (config->has_l3_cache) {
+ if (!mc->smp_props.l2_unified_cache_supported) {
+ error_setg(errp,
+ "L3 cache topology not supported by this machine");
+ return;
+ }
+
+ if (!machine_check_cache_topo(ms, config->l3_cache, errp)) {
+ return;
+ }
+
+ ms->smp_cache.l3 = config->l3_cache;
+
+ if (ms->smp_cache.l1d > ms->smp_cache.l3 ||
+ ms->smp_cache.l1i > ms->smp_cache.l3 ||
+ ms->smp_cache.l2 > ms->smp_cache.l3) {
+ error_setg(errp,
+ "Invalid L3 cache topology. "
+ "L3 cache topology level should not be lower than "
+ "L1 D-cache/L1 I-cache/L2 cache");
+ return;
+ }
+ }
+}
+
/*
* machine_parse_smp_config: Generic function used to parse the given
* SMP configuration
@@ -259,6 +403,8 @@ void machine_parse_smp_config(MachineState *ms,
mc->name, mc->max_cpus);
return;
}
+
+ machine_parse_smp_cache_config(ms, config, errp);
}
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index e31d0f3cb4b0..f705485f83c0 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -900,6 +900,26 @@ static void machine_get_smp(Object *obj, Visitor *v, const char *name,
.has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
};
+ if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) {
+ config->has_l1d_cache = true;
+ config->l1d_cache = ms->smp_cache.l1d;
+ }
+
+ if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) {
+ config->has_l1i_cache = true;
+ config->l1i_cache = ms->smp_cache.l1i;
+ }
+
+ if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) {
+ config->has_l2_cache = true;
+ config->l2_cache = ms->smp_cache.l2;
+ }
+
+ if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) {
+ config->has_l3_cache = true;
+ config->l3_cache = ms->smp_cache.l3;
+ }
+
if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
return;
}
diff --git a/qapi/machine.json b/qapi/machine.json
index 7ac5a05bb9c9..8fa5af69b1bf 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1746,6 +1746,23 @@
#
# @threads: number of threads per core
#
+# @l1d-cache: topology hierarchy of L1 data cache. It accepts the CPU
+# topology enumeration as the parameter, i.e., CPUs in the same
+# topology container share the same L1 data cache. (since 9.1)
+#
+# @l1i-cache: topology hierarchy of L1 instruction cache. It accepts
+# the CPU topology enumeration as the parameter, i.e., CPUs in the
+# same topology container share the same L1 instruction cache.
+# (since 9.1)
+#
+# @l2-cache: topology hierarchy of L2 unified cache. It accepts the CPU
+# topology enumeration as the parameter, i.e., CPUs in the same
+# topology container share the same L2 unified cache. (since 9.1)
+#
+# @l3-cache: topology hierarchy of L3 unified cache. It accepts the CPU
+# topology enumeration as the parameter, i.e., CPUs in the same
+# topology container share the same L3 unified cache. (since 9.1)
+#
# Since: 6.1
##
{ 'struct': 'SMPConfiguration', 'data': {
@@ -1758,7 +1775,11 @@
'*modules': 'int',
'*cores': 'int',
'*threads': 'int',
- '*maxcpus': 'int' } }
+ '*maxcpus': 'int',
+ '*l1d-cache': 'CPUTopoLevel',
+ '*l1i-cache': 'CPUTopoLevel',
+ '*l2-cache': 'CPUTopoLevel',
+ '*l3-cache': 'CPUTopoLevel' } }
##
# @x-query-irq:
diff --git a/system/vl.c b/system/vl.c
index a3eede5fa5b8..c7c94d41bd01 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -753,6 +753,18 @@ static QemuOptsList qemu_smp_opts = {
}, {
.name = "maxcpus",
.type = QEMU_OPT_NUMBER,
+ }, {
+ .name = "l1d-cache",
+ .type = QEMU_OPT_STRING,
+ }, {
+ .name = "l1i-cache",
+ .type = QEMU_OPT_STRING,
+ }, {
+ .name = "l2-cache",
+ .type = QEMU_OPT_STRING,
+ }, {
+ .name = "l3-cache",
+ .type = QEMU_OPT_STRING,
},
{ /*End of list */ }
},
diff --git a/tests/unit/meson.build b/tests/unit/meson.build
index 26c109c968ce..8877dbbc00c9 100644
--- a/tests/unit/meson.build
+++ b/tests/unit/meson.build
@@ -138,7 +138,8 @@ if have_system
'test-util-sockets': ['socket-helpers.c'],
'test-base64': [],
'test-bufferiszero': [],
- 'test-smp-parse': [qom, meson.project_source_root() / 'hw/core/machine-smp.c'],
+ 'test-smp-parse': [qom, meson.project_source_root() / 'hw/core/machine-smp.c',
+ meson.project_source_root() / 'hw/core/cpu-topology.c'],
'test-vmstate': [migration, io],
'test-yank': ['socket-helpers.c', qom, io, chardev]
}
--
2.34.1
