On Wed, Mar 13, 2024 at 02:27:18PM +0100, Gerd Hoffmann wrote:
> Query kvm for supported guest physical address bits, in cpuid
> function 80000008, eax[23:16]. Usually this is identical to host
> physical address bits. With NPT or EPT being used this might be
> restricted to 48 (max 4-level paging address space size) even if
> the host cpu supports more physical address bits.
>
> When set pass this to the guest, using cpuid too. Guest firmware
> can use this to figure how big the usable guest physical address
> space is, so PCI bar mapping are actually reachable.
>
> Signed-off-by: Gerd Hoffmann <kraxel@xxxxxxxxxx>
> ---
> target/i386/cpu.h | 1 +
> target/i386/cpu.c | 1 +
> target/i386/kvm/kvm-cpu.c | 32 +++++++++++++++++++++++++++++++-
> 3 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 952174bb6f52..d427218827f6 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2026,6 +2026,7 @@ struct ArchCPU {
>
> /* Number of physical address bits supported */
> uint32_t phys_bits;
> + uint32_t guest_phys_bits;
>
> /* in order to simplify APIC support, we leave this pointer to the
> user */
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 9a210d8d9290..c88c895a5b3e 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
> /* 64 bit processor */
> *eax |= (cpu_x86_virtual_addr_width(env) << 8);
> + *eax |= (cpu->guest_phys_bits << 16);
> }
> *ebx = env->features[FEAT_8000_0008_EBX];
> if (cs->nr_cores * cs->nr_threads > 1) {
> diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
> index 9c791b7b0520..a2b7bfaeadf8 100644
> --- a/target/i386/kvm/kvm-cpu.c
> +++ b/target/i386/kvm/kvm-cpu.c
> @@ -18,10 +18,36 @@
> #include "kvm_i386.h"
> #include "hw/core/accel-cpu.h"
>
> +static void kvm_set_guest_phys_bits(CPUState *cs)
> +{
> + X86CPU *cpu = X86_CPU(cs);
> + uint32_t eax, guest_phys_bits;
> +
> + if (!cpu->host_phys_bits) {
> + return;
> + }
> +
> + eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x80000008, 0, R_EAX);
> + guest_phys_bits = (eax >> 16) & 0xff;
> + if (!guest_phys_bits) {
> + return;
> + }
> +
> + if (cpu->guest_phys_bits == 0 ||
> + cpu->guest_phys_bits > guest_phys_bits) {
> + cpu->guest_phys_bits = guest_phys_bits;
> + }
> +
> + if (cpu->guest_phys_bits > cpu->host_phys_bits_limit) {
> + cpu->guest_phys_bits = cpu->host_phys_bits_limit;
host_phys_bits_limit is zero by default, so I think it is better to be
like:
if (cpu->host_phys_bits_limit &&
cpu->guest_phys_bits > cpu->host_phys_bits_limit) {
cpu->guest_phys_bits = cpu->host_phys_bits_limit;
}
> + }
> +}
> +
> static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
> {
> X86CPU *cpu = X86_CPU(cs);
> CPUX86State *env = &cpu->env;
> + bool ret;
>
> /*
> * The realize order is important, since x86_cpu_realize() checks if
> @@ -50,7 +76,11 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
> MSR_IA32_UCODE_REV);
> }
> }
> - return host_cpu_realizefn(cs, errp);
> + ret = host_cpu_realizefn(cs, errp);
> +
> + kvm_set_guest_phys_bits(cs);
> +
> + return ret;
> }
>
> static bool lmce_supported(void)
> --
> 2.44.0
>
>
