Intel Linear-address masking (LAM) [1], modifies the checking that is applied to *64-bit* linear addresses, allowing software to use of the untranslated address bits for metadata. The patch series add test cases for KVM LAM: Patch 1 makes change to allow setting of CR3 LAM bits in vmlaunch tests. Patch 2~4 add test cases for LAM supervisor mode and user mode, including: - For supervisor mode CR4.LAM_SUP toggle Memory/MMIO access with tagged pointer INVLPG INVPCID INVVPID (also used to cover VMX instruction VMExit path) - For user mode CR3 LAM bits toggle Memory/MMIO access with tagged pointer [1] Intel ISE https://cdrdv2.intel.com/v1/dl/getContent/671368 Chapter Linear Address Masking (LAM) --- Changelog v6 - Fix a comment [Chao] - Use write_cr4() instead of write_cr4_safe() to catch unexpected exceptions. [Chao] - Use a non-canonical address that will be canonical if LAM applied as the tagged address in the descriptor of invvpid. [Chao] - Add a reviewed-by from Chao in patch 4. v5 - https://lore.kernel.org/kvm/20230530024356.24870-1-binbin.wu@xxxxxxxxxxxxxxx/ Binbin Wu (3): x86: Allow setting of CR3 LAM bits if LAM supported x86: Add test cases for LAM_{U48,U57} x86: Add test case for INVVPID with LAM Robert Hoo (1): x86: Add test case for LAM_SUP lib/x86/processor.h | 15 +++ x86/Makefile.x86_64 | 1 + x86/lam.c | 319 ++++++++++++++++++++++++++++++++++++++++++++ x86/unittests.cfg | 10 ++ x86/vmx_tests.c | 52 +++++++- 5 files changed, 395 insertions(+), 2 deletions(-) create mode 100644 x86/lam.c base-commit: 3c1736b1344b9831f17fbd64f95ea89c279564c6 -- 2.25.1
