On Thu, Dec 07, 2023 at 09:38:25AM -0400, Jason Gunthorpe wrote: > On Thu, Dec 07, 2023 at 11:13:52AM +0100, Lorenzo Pieralisi wrote: > > > > What about the other way around - would we have a prefetchable BAR that > > > > has portions which are unprefetchable? > > > > > > I would say possibly. > > > > > > Prefetch is a dead concept in PCIe, it was obsoleted in PCI-X about 20 > > > years ago. No PCIe system has ever done prefetch. > > > > > > There is a strong incentive to mark BAR's as prefetchable because it > > > allows 64 bit addressing in configurations with bridges. > > > > If by strong incentive you mean the "Additional guidance on the > > Prefetchable Bit in Memory Space BARs" in the PCI express specifications, > > I think it has been removed from the spec and the criteria that had to be > > met to implement it were basically impossible to fulfill on ARM systems, > > it did not make any sense in the first place. > > No, I mean many systems don't have room to accommodate large 32 bit > BARs and the only real way to make stuff work is to have a 64 bit BAR > by setting prefetchable. That's what the implementation note I mentioned referred to ;) > Given mis-marking a read-side-effect region as prefetchable has no > actual consequence on PCI-E I would not be surprised to learn people > have done this. PCIe specs 6.1, 7.5.1.2.1 "Base Address Registers" "A function is permitted to mark a range as prefetchable if there are no side effects on reads..." I don't think that an OS should use the prefetchable flag to infer anything (even though we do at the moment -> sysfs mappings, I know that the prefetchable concept is being scrapped from the PCI specs altogether for a reason), I don't see though how we can say that's a SW bug at present given what I quoted above. I'd agree that it is best not to use that flag for new code we are adding (because it will be deprecated soon). Thanks, Lorenzo
