On Wed, Oct 25, 2023 at 09:28:03AM +0100, Marc Zyngier wrote: > On Wed, 25 Oct 2023 00:04:27 +0100, Oliver Upton <oliver.upton@xxxxxxxxx> wrote: > > Correction (I wasn't thinking): RES0 behavior should be invariant, much > > like the UNDEF behavior of the other AA32-specific registers. > > I'm not sure what you're asking for exactly here, so let me explain my > understanding of the architecture on this point, which is that the > *32_EL2 registers are different in nature from the SPSR_* registers. Damn, I still didn't manage to get my point across! > IFAR32_EL2 and co are accessors for the equivalent AArch32 registers. > If AArch32 isn't implemented, then these registers should UNDEF, > because there is nothing to access at all. > > The status of SPSR_* is more subtle: the AArch32 exception model is > banked (irq, fiq, abt, und), and for each bank we have a triplet > (LR_*, SP_*, SPSR_*), plus the extra R[8-12]_fiq. On taking an > exception from AArch32 EL1 to AArch64 EL2, all the (LR_*, SP_*, > R*_fiq) are stored as part of the AArch64 GPRs (X16-X30, see I_PYKVS). Thanks. Yeah, I've got a pretty good handle on what's going on here. What I really was trying to compare is the way these aliases into AA32 state are handled, and the annoying difference between the two sets. IFAR32 and friends UNDEF unconditionally w/o AArch32, which I quite like. To your point, the SPSR_* accessors still trap even if AArch32 is not implemented. I was suggesting in passing that it'd be nice if the architecture alternatively allowed for these to read as RES0 (no trap) if NV==1 and AArch32 is not implemented, which aligns with your change. But after all... > we will never see an AArch32-capable, NV-capable HW implementation > ever, so this is all fairly academic. None of this matters in the first place :) -- Thanks, Oliver
